CY7C027V-15AXI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C027V-15AXI Datasheet PDF : 24 Pages
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CY7C027V/027AV/028V
CY7C037AV/038V
Selection Guide
Parameter
Maximum access time
Typical operating current
Typical standby current for ISB1 (Both ports TTL level)
Typical standby current for ISB3 (Both ports CMOS level)
-15
-20
-25
Unit
15
20
25
ns
125
120
115
mA
35
35
30
mA
10
10
10
A
Pin Definitions
Left Port
CE0L, CE1L
R/WL
OEL
A0L–A15L
I/O0L–I/O17L
SEML
UBL
LBL
INTL
BUSYL
M/S
VCC
GND
NC
Right Port
CE0R, CE1R
R/WR
OER
A0R–A15R
I/O0R–I/O17R
SEMR
UBR
LBR
INTR
BUSYR
Description
Chip Enable (CE is LOW when CE0 VIL and CE1 VIH)
Read/Write Enable
Output Enable
Address (A0–A14 for 32K; A0–A15 for 64K devices)
Data bus input/output (I/O0–I/O15 for × 16 devices; I/O0–I/O17 for × 18)
Semaphore Enable
Upper byte select (I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices)
Lower byte select (I/O0–I/O7 for × 16 devices; I/O0–I/O8 for × 18 devices)
Interrupt flag
Busy flag
Master or Slave select
Power
Ground
No connect
Architecture
The CY7C027V/027AV/028V and CY7037AV/038V consist of an
array of 32K and 64K words of 16 and 18 bits each of dual-port
RAM cells, I/O and address lines, and control signals (CE, OE,
R/W). These control pins permit independent access for reads or writes
to any location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two interrupt (INT)
pins can be utilized for port-to-port communication. Two semaphore
(SEM) control pins are used for allocating shared resources. With the
M/S pin, the devices can function as a master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The devices also have an
automatic power down feature controlled by CE. Each port is provided
with its own output enable control (OE), which allows data to be read
from the device.
Functional Description
The CY7C027V/027AV/028V and CY7037AV/038V are low
power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various
arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as stand-alone 16/18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32/36-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 32/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the other
port. The interrupt flag (INT) permits communication between ports or
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The CY7C027V/027AV/028V and CY7037AV/038V are
available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs
Document Number: 38-06078 Rev. *G
Page 5 of 24
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