CY7C008V(2010) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C008V Datasheet PDF : 23 Pages
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CY7C008V/009V
CY7C018V/019V
AC Test Loads and Waveforms
3.3 V
OUTPUT
C = 30 pF
R1 = 590
R2 = 435
OUTPUT
C = 30 pF
RTH = 250
OUTPUT
VTH = 1.4 V
C = 5 pF
3.3 V
R1 = 590
R2 = 435
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0 V
GND
10%
3 ns
90%
90%
10%
3 ns
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
Switching Characteristics
Over the Operating Range[11]
Parameter
Description
READ CYCLE
tRC
tAA
tOHA
tACE[12]
tDOE
tLZOE[13, 14, 15]
tHZOE[13, 14, 15]
tLZCE[13, 14, 15]
tHZCE[13, 14, 15]
tPU[15]
tPD[15]
tABE[12]
Read cycle time
Address to data valid
Output hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Byte enable access time
CY7C018V/019V
–15
–20
–25
Unit
Min Max Min Max Min Max
15
–
20
–
25
–
ns
–
15
–
20
–
25
ns
3
–
3
–
3
–
ns
–
15
–
20
–
25
ns
–
10
–
12
–
13
ns
3
–
3
–
3
–
ns
–
10
–
12
–
15
ns
3
–
3
–
3
–
ns
–
10
–
12
–
15
ns
0
–
0
–
0
–
ns
–
15
–
20
–
25
ns
–
15
–
20
–
25
ns
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOI/IOH and 30 pF load capacitance.
12. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Read Timing with Busy waveform.
Document Number: 38-06044 Rev. *E
Page 8 of 23
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