CY62256VN(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62256VN
(Rev.:2011)

256K (32K × 8) Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Figure 6. Write Cycle No. 2 (CE Controlled)[21, 22, 23]

ADDRESS

CE

WE

DATA I/O

tWC

tSCE

tSA

tAW

tHA

tSD

t HD

DATAINVALID

ADDRESS

Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)[23, 24]

tWC

CE

WE

DATA I/O

tAW

tSA

NOTE 25

t HZWE

t HA

tSD

DATA INVALID

t HD

tLZWE

CY62256VN

Notes

21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

22. Data I/O is high impedance if OE = VIH.

23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

24. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

25. During this period, the I/Os are in output state and input signals should not be applied.

Document Number: 001-06512 Rev. *D

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