CY2305C Просмотр технического описания (PDF) - Cypress Semiconductor
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CY2305C Datasheet PDF : 17 Pages
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CY2305C
CY2309C
Table 2. Pin Definition - 16 Pin SOIC/TSSOP (continued)
Pin
Signal
9
S1[4]
10
CLKB3[5]
11
CLKB4[5]
12
GND
13
VDD
14
CLKA3[5]
15
CLKA4[5]
16
CLKOUT[5]
Description
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3 V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Table 3. Select Input Decoding for CY2309C
S2
S1
CLOCK A1–A4 CLOCK B1–B4
0
0
Three state
Three state
0
1
Driven
Three state
1
0
Driven
Driven
1
1
Driven
Driven
Zero Delay and Skew Control
CLKOUT[6]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
For zero output to output skew, all outputs must be loaded
equally.
Notes
4. Weak pull ups on these inputs.
5. Weak pull down on all outputs.
6. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *K
Page 5 of 17
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