CY2213(2012) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY2213 Datasheet PDF : 16 Pages
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CY2213
CLK
Figure 10. Duty Cycle Jitter
CLKB
tPW+
tCYCLE
DC = tPW+/tCYCLE
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 11 shows the definition of period jitter with respect to the
falling edge of the CLK signal. Period jitter is the difference
between the minimum and maximum cycle times over many
cycles (typically 12,800 cycles at 400 MHz). Equal requirements
apply for rising edges of the CLK signal. tJP is defined as the
output period jitter.
Figure 12 shows the definition of cycle-to-cycle jitter with respect
to the falling edge of the CLK signal. Cycle-to-cycle jitter is the
difference between cycle times of adjacent cycles over many
cycles (typically 12,800 cycles at 400 MHz). Equal requirements
apply for rising edges of the CLK signal. tJC is defined as the
Clock Output Cycle-to-cycle Jitter.
Figure 13 on page 11 shows the definition of cycle-to-cycle duty
cycle error. Cycle-to-cycle duty cycle error is defined as the
difference between high-times of adjacent cycles over many
cycles (typically 12,800 cycles at 400 MHz). Equal requirements
apply to the low-times. tDC,ERR is defined as the Clock Output
Cycle-to-cycle Duty Cycle Error.
Figure 14 on page 11 shows the definition of long-term jitter error.
Long term jitter is defined as the accumulated timing error over
many cycles (typically 12,800 cycles at 400 MHz). It applies to
both rising and falling edges. tJLT is defined as the long term jitter.
CLK
Figure 11. Period Jitter
CLKB
CLK
tCYCLE
tJP = tCYCLE,max – tCYCLE, min. over many cycles
Figure 12. Cycle-to-cycle Jitter
CLKB
tCYCLE,i
tCYCLE, i+1
tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles
Document Number: 38-07263 Rev. *H
Page 10 of 16
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