CY14B256L-SZ25XI(2007) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B256L-SZ25XI Datasheet PDF : 17 Pages
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PRELIMINARY
CY14B256L
AC Switching Characteristics
Parameter
Cypress
Parameter
Alt.
Parameter
SRAM READ Cycle
Description
25 ns part
Min Max
tACE
tRC [8]
tAA [9]
tACS
tRC
tAA
tDOE
tOHA [9]
tLZCE [10]
tHZCE [10]
tLZOE [10]
tHZOE [10]
tPU [7]
tPD [7]
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
SRAM WRITE Cycle
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tHZWE [10, 11]
tLZWE [10]
tWR
tWZ
tOW
Chip Enable Access Time
25
Read Cycle Time
25
Address Access Time
25
Output Enable to Data Valid
12
Output Hold After Address Change 3
Chip Enable to Output Active
3
Chip Disable to Output Inactive
10
Output Enable to Output Active
0
Output Disable to Output Inactive
10
Chip Enable to Power Active
0
Chip Disable to Power Standby
25
Write Cycle Time
25
Write Pulse Width
20
Chip Enable To End of Write
20
Data Setup to End of Write
10
Data Hold After End of Write
0
Address Setup to End of Write
20
Address Setup to Start of Write
0
Address Hold After End of Write
0
Write Enable to Output Disable
10
Output Active after End of Write
3
35 ns part
Min Max
45 ns part
Unit
Min Max
35
45 ns
35
45
ns
35
45 ns
15
20 ns
3
3
ns
3
3
ns
13
15 ns
0
0
ns
13
15 ns
0
0
ns
35
45 ns
35
45
ns
25
30
ns
25
30
ns
12
15
ns
0
0
ns
25
30
ns
0
0
ns
0
0
ns
13
15 ns
3
3
ns
Notes
8. WE must be HIGH during SRAM READ Cycles.
9. Device is continuously selected with CE and OE both Low.
10. Measured ± 200 mV from steady state output voltage.
Document #: 001-06422 Rev. *E
Page 9 of 17
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