CY14B104NA-BA25IT Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B104NA-BA25IT Datasheet PDF : 26 Pages
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CY14B104LA, CY14B104NA
4-Mbit (512 K × 8/256 K × 16) nvSRAM
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512 K × 8 (CY14B104LA) or 256 K × 16
(CY14B104NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20, –10 operation
■ Industrial temperature
■ Packages
❐ 44-/54-pin thin small outline package (TSOP) Type II
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a non-volatile element in each memory cell. The
memory is organized as 512 K bytes of 8 bits each or 256 K
words of 16-bits each. The embedded non-volatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable non-volatile memory. The SRAM provides infinite
read and write cycles, while independent non-volatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the non-volatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the non-volatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram [1, 2, 3]
A0
R
A1
O
A2
W
A3
A4
D
A5
E
A6
C
A7
A8
A17
O
D
E
A18
R
DQ0
DQ1
DQ2
DQ3
DQ4
I
N
DQ5
P
DQ6
U
T
DQ7
B
DQ8
U
F
DQ9
F
DQ10
E
R
DQ11
S
DQ12
DQ13
DQ14
DQ15
Quatrum Trap
2048 X 2048
STORE
RECALL
STATIC RAM
ARRAY
2048 X 2048
COLUMN I/O
COLUMN DEC
A9 A10 A11 A12 A13 A14 A15 A16
VCC
VCAP
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-49918 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2012
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