CY14B104KA Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B104KA Datasheet PDF : 31 Pages
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PRELIMINARY
CY14B104KA, CY14B104MA
Pin Definitions (continued)
Pin Name IO Type
Description
INT
Output
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
VCC
HSB
Ground Ground for the Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
is driven HIGH for short time with standard output high current.
VCAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14B104KA/CY14B104MA nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104KA/CY14B104MA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the “Truth Table For SRAM Operations” on
page 23 for a complete description of read and write modes.
SRAM Read
The CY14B104KA/CY14B104MA performs a read cycle
whenever CE and OE are LOW, and WE and HSB are HIGH.
The address specified on pins A0-18 or A0-17 determines which
of the 524,288 data bytes or 262,144 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for transi-
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DO0-15 are
written into the memory if it is valid tSD before the end of a WE
controlled write or before the end of a CE controlled write. The
Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. Keep OE HIGH during the
entire write cycle to avoid data bus contention on common IO
lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B104KA/CY14B104MA stores data to the nvSRAM
using one of three storage operations. These three operations
are: hardware store, activated by the HSB; software store,
activated by an address sequence; AutoStore, on device power
down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104KA/CY14B104MA.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2. AutoStore Mode
Vcc
0.1uF
Vcc
WE
VCAP
VSS
VCAP
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 14 for the size of the VCAP. The voltage
on the VCAP pin is driven to VCC by a regulator on the chip. A pull
up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during
Document #: 001-07103 Rev. *J
Page 3 of 31
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