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CY14B104M(2009) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание
производитель
CY14B104M
(Rev.:2009)
Cypress
Cypress Semiconductor Cypress
CY14B104M Datasheet PDF : 33 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power down
RECALL to SRAM is initiated by software or power up
High reliability
Infinite Read, Write, and RECALL cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, –10% operation
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Commercial and industrial temperatures
44 and 54-pin TSOP II package
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B104K and CY14B104M combines a 4 Mbit
nonvolatile static RAM with a full featured RTC in a monolithic
integrated circuit. The embedded nonvolatile elements incor-
porate QuantumTrap technology producing the world’s most
reliable nonvolatile memory. The SRAM is read and written
infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Logic Block Diagram[1, 2, 3]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
A18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Quatrum
Trap
VCC
VCA
P
2048 X 2048
R
O
STORE
POWER
CONTROL
VRTCbat
VRTCcap
W
RECALL
D
E
STATIC RAM
C
ARRAY
O
2048 X 2048
D
E
R
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
I
N
P
U
T
B
COLUMN I/O
U
F
F
E
R
COLUMN DEC
S
A9 A10 A11 A12 A13 A14 A15 A16
RTC
MUX
Xout
Xin
INT
A18- A0
OE
WE
CE
BLE
BHE
Notes
1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07103 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 15, 2009
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