CXK77V3211Q Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXK77V3211Q

32768-word by 32-bit High Speed Synchronous Static RAM

Sony Semiconductor 

Interleaved Burst Sequence Table

Operation

First access, latch external address

Second access (first burst address)

Third access (second burst address)

Fourth access (third burst address)

A14 to A2

A14 to A2

latched A14 to A2

latched A14 to A2

latched A14 to A2

Address used

A1

A1

latched A1

latched A1

latched A1

CXK77V3211Q

A0

A0

latched A0

latched A0

latched A0

Interleaved Burst Address Table

First address Second address

X...X00

X...X01

X...X01

X...X00

X...X10

X...X11

X...X11

X...X10

Third address

X...X10

X...X11

X...X00

X...X01

Fourth address

X...X11

X...X10

X...X01

X...X00

Linear Burst Address Table

First address Second address

X...X00

X...X01

X...X01

X...X10

X...X10

X...X11

X...X11

X...X00

Third address

X...X10

X...X11

X...X00

X...X01

Fourth address

X...X11

X...X00

X...X01

X...X10

Pass-Through Truth Table

Previous cycle

Present cycle

Next cycle

Operation

BWs

Operation

CE BWs OE

Operation

Initial WRITE cycle, all bytes

Address = A (n – 1),

data = D (n – 1)

All L

Initial READ cycle

Register A (n), Q = D (n – 1)

L

H

L Read D (n)

Initial WRITE cycle, all bytes

Address = A (n – 1),

data = D (n – 1)

All L

No new cycle

Q = D (n – 1)

H

H

L

No carryover from

previous cycle

Initial WRITE cycle, all bytes

Address = A (n – 1),

data = D (n – 1)

All L

No new cycle

Q = HIGH-Z

H

H

H

No carryover from

previous cycle

Initial WRITE cycle, one byte

Address = A (n – 1),

data = D (n – 1)

One L

No new cycle

Q = D (n – 1) for one byte

H

H

L

No carryover from

previous cycle

Note) Previous cycle may be either BURST or NONBURST cycle.

–5–

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