CXK77V3211Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXK77V3211Q

32768-word by 32-bit High Speed Synchronous Static RAM

Sony Semiconductor 

CXK77V3211Q

Pin Description

Symbol

I/O

Description

A0 to A14

BW1, BW2,

BW3, BW4

CLK

CE

CE2

CE2

OE

ADV

ADSP

ADSC

NC

DQ1 to DQ32

BWE

SGW

FT

LBO

ZZ

VDD

VSS

VDDq

VSSq

I

I

I

I

I

I

I

I

I

I

—

I/O

I

I

I

I

I

Supply

Supply

Supply

Supply

Synchronous Address Inputs: These inputs are registered and must meet the

setup and hold times around the rising edge of CLK.

Synchronous Individual Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold times around the

rising edge of CLK. A BYTE WRITE enable is LOW for a WRITE cycle and HIGH

for a READ cycle. BW1 controls DQ1 to DQ8. BW2 controls DQ9 to DQ16. BW3

controls DQ17 to DQ24. BW4 controls DQ25 to DQ32. Data I/O are tristated if

any of these four inputs are LOW.

Clock: This signal latches the address, data, chip enable, byte write enables and

burst control inputs on its rising edge. All synchronous inputs must meet setup

and hold times around the clock's rising edge.

Synchronous Chip Enable: This active LOW input is used to enable the device

and conditions internal use of ADSP. This input is sampled only when a new

external address is loaded.

Synchronous Chip Enable: This active LOW input is used to enable the device.

This input is sampled only when a new external address is loaded. This input can

be used for memory depth expansion.

Synchronous Chip Enable: This active HIGH input is used to enable the device.

This input is sampled only when a new external address is loaded. This input can

be used for memory depth expansion.

Output Enable: This active LOW asynchronous input enables the data I/O output

drivers.

Synchronous Address Advance: This active LOW input is used to advance the

internal burst counter, controlling burst access after the external address is

loaded. A HIGH on this pin effectively causes wait status to be generated (no

address advance). This pin must be HIGH at the rising edge of the first clock after

an ADSP cycle is initiated if a WRITE cycle is desired (to ensure use of correct

address).

Synchronous Address Status Processor: This active LOW input interrupts any

ongoing burst, causing a new external address to be latched. A READ is

performed using the new address, independent of the byte write enables and

ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE is HIGH. Power

down state is entered if CE2 is LOW or CE2 is HIGH.

Synchronous Address Status Controller: This active LOW input interrupts any

ongoing burst and causes a new external address to be latched. A READ or

WRITE is performed using the new address if all chip enables are active. Power-

down state is entered if one or more chip enables are inactive.

No Connect: These signals are not internally connected.

SRAM Data I/O: Byte 1 is DQ1 to DQ8; Byte 2 is DQ9 to DQ16; Byte 3 is DQ17 to

DQ24; Byte 4 is DQ25 to DQ32. Input data must meet setup and hold times

around the rising edge of CLK.

Byte Write Enable: This active low input enables individual byte to write.

Global Write: This active low input enables to write all bytes.

Flow Through: This active low input selects flow through output.

Linear Burst: This active high input selects interleaved burst sequence.

ZZ: This active high input enables the device in powerdown mode.

Power

Supply:

+3.3V

+10%

– 5%

Ground: GND

Isolated

Output

Buffer

Supply:

+3.3V

+10%

– 5%

Isolated Output Buffer Ground: GND

–4–

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