CXK77V3211Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXK77V3211Q Datasheet PDF : 18 Pages
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CXK77V3211Q
Truth Tables
Operation
Address
used
Deselected cycle, power-down None
Deselected cycle, power-down None
Deselected cycle, power-down None
Deselected cycle, power-down None
Deselected cycle, power-down None
READ cycle, begin burst
External
READ cycle, begin burst
External
WRITE cycle, begin burst
External
READ cycle, begin burst
External
READ cycle, begin burst
External
READ cycle, continue burst
Next
READ cycle, continue burst
Next
READ cycle, continue burst
Next
READ cycle, continue burst
Next
WRITE cycle, continue burst Next
WRITE cycle, continue burst Next
READ cycle, suspend burst
Current
READ cycle, suspend burst
Current
READ cycle, suspend burst
Current
READ cycle, suspend burst
Current
WRITE cycle, suspend burst Current
WRITE cycle, suspend burst Current
CE CE2 CE2 ADSP ADSC ADV BWx OE CLK DQ
HXX X
L XL
L
L HX L
LXL H
L HX H
L LH L
L LH L
L LH H
L LH H
L LH H
XXX H
XXX H
HXX X
HXX X
XXX H
HXX X
XXX H
XXX H
HXX X
HXX X
XXX H
HXX X
L X X X L-H High-Z
X X X X L-H High-Z
X X X X L-H High-Z
L X X X L-H High-Z
L X X X L-H High-Z
X X X L L-H Q
X X X H L-H High-Z
L X L X L-H D
L X H L L-H Q
L X H H L-H High-Z
H L H L L-H Q
H L H H L-H High-Z
H L H L L-H Q
H L H H L-H High-Z
H L L X L-H D
H L L X L-H D
H H H L L-H Q
H H H H L-H High-Z
H H H L L-H Q
H H H H L-H High-Z
H H L X L-H D
H H L X L-H D
Note) 1. X means "don't care". H means logic HIGH. L means logic LOW. BWx = L means any one or more
byte write enable signals (BW1, BW2, BW3, BW4) are LOW. BWx = H means all byte write enable
signals are HIGH.
2. BW1 enables writes to Byte 1 (DQ1 to DQ8). BW2 enables writes to Byte 2 (DQ9 to DQ16). BW3
enables writes to Byte 3 (DQ17 to DQ24). BW4 enables writes to Byte 4 (DQ25 to DQ32).
3. All inputs except OE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Wait states are inserted by suspending burst.
5. For a write operation following a read operation, OE must be HIGH before the input data required
setup time and held HIGH throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in HIGH-Z during power-up.
7. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by
setting one or more byte write enable signals LOW for the subsequent L-H edge of CLK. Refer to
WRITE timing diagram for clarification.
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