CXK5V16100TM Просмотр технического описания (PDF) - Sony Semiconductor
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CXK5V16100TM Datasheet PDF : 10 Pages
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CXK5V16100TM
• Read cycle (WE = “H”)
-85LLX
-10LLX
Item
Symbol
Unit
Min. Max. Min. Max.
Read cycle time
tRC
85
—
100
— ns
Address access time
Chip enable access time (CE)
tAA
—
85
—
100 ns
tCO
—
85
—
100 ns
Byte enable access time (UB, LB)
tBO
—
40
—
50 ns
Output enable to output valid
Output hold from address change
tOE
—
40
—
50 ns
tOH
10
—
10
— ns
Chip enable to output in low Z (CE)
tLZ
10
—
10
— ns
Ouput enable to output in low Z (OE)
tOLZ
5
—
5
— ns
Byte enable to output in low Z (UB, LB) tBLZ
5
—
5
— ns
Chip disable to output in high Z (CE)
tHZ∗
—
35
—
40 ns
Chip disable to output in high Z (OE)
tOHZ∗
—
30
—
35 ns
Byte disable to output in high Z (UB, LB) tBHZ∗
—
30
—
35 ns
∗ tHZ, tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
-85LLX
-10LLX
Item
Symbol
Unit
Min. Max. Min. Max.
Write cycle time
tWC
85
—
100
— ns
Address valid to end of write
tAW
70
—
80
— ns
Chip enable to end of write
tCW
70
—
80
— ns
Byte enable to end of write
tBW
70
—
80
— ns
Data to write time overlap
tDW
35
—
40
— ns
Data hold from write time
tDH
0
—
0
— ns
Write pulse width
tWP
60
—
70
— ns
Address setup time
tAS
0
—
0
— ns
Write recovery time (WE)
tWR
5
—
5
— ns
Write recovery time (CE, UB, LB)
tWR1
5
—
5
— ns
Output active from end of write
Write to output in high Z
tOW
5
—
5
— ns
tWHZ∗
—
35
—
40 ns
∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage levels.
–5–
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