CXD4017R
(3) SCLK, XSCEN, SWDT, SRDT pins
(VDDE = 2.5 ± 0.2V, VDDI = 1.5 ± 0.1V, VSS = 0V, Topr = –40 to +85°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Clock period
tCW
800
—
—
ns
Clock pulse width, high tCWH
400
—
—
ns
Clock pulse width, low tCWL
400
—
—
ns
Enable signal pulse width tCSWH
170
—
—
ns
Enable signal setup time tCSS
0
—
—
ns
Enable signal hold time tCSH
400
—
—
ns
Setup time
tWSU
350
—
—
ns
Hold time
tWHD
350
—
—
ns
Access time
tAC
—
—
345
ns
Enable time
tOLZ
162
—
—
ns
Disable time
tOHZ
—
—
80
ns
XSCEN
tCSS
tCW
tCWL tCWH
tCSH tCSWH
SCLK
SWDT
tWSU tWHD
An Example of DATA READ Phase
Hi-Z
SRDT
Valid
Hi-Z
Valid
tAC
tOLZ
tAC
tOHZ
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