CXD1196 Просмотр технического описания (PDF) - Sony Semiconductor
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CXD1196 Datasheet PDF : 28 Pages
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CXD1196AR
2. SRAM interface
(1) Read
MA14-MA0
Tsao
Toel
Thao
XMOE
MDB7-MDB0
Item
Address setting time (with respect to XMOE ↓)
Address holding time (with respect to XMOE ↑)
Data setting time (with respect to XMOE ↑)
Data holding time (with respect to XMOE ↑)
L level XMOE pulse width
Tsdo
Thdo
Symbol Min.
Typ.
Max.
Unit
Tsao T1–30
ns
Thao T1–10
ns
Tsdo 50 (100)
ns
Thdo 10 (20)
ns
Toel
2 • T1
ns
(2) Write
MA14-MA0
XMWR
Tsamw
Tmwl
Thamw
MDB7-MDB0
Tdmw
Tfmw
Item
Address setting time (with respect to XMWR ↓)
Address holding time (with respect to XMWR ↑)
Data delay time (with respect to XMWR ↓)
Data float time (with respect to XMWR ↑)
L level XMWR pulse width
Symbol Min.
Typ.
Max.
Unit
Tsamw T1–30
ns
Thamw T1–10
ns
Tdmw
0
ns
Tfmw
10
ns
Tmwl
2 • T1
ns
{ 59 ns : XSLOW = ‘H’
T1=
238 ns : XSLOW = ‘L’
Note that XSLOW is bit 7 of DRVIF register.
When XSLOW = ‘H’ , make sure that the CXD1196AR is connected to an SRAM with an access time of
less than 120 ns.
When XSLOW = ‘L’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less
than 320 ns.
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