CX81801-8X Просмотр технического описания (PDF) - Conexant Systems

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CX81801-8X

SmartV.XX Modem

Conexant Systems 

CX81801-7x/8x SmartV.XX Modem Data Sheet

3.1.2 Serial Interface Configuration Only................................................................................................................. 3-2

3.1.2.1 Serial DTE Interface and Indicator Outputs (PARIF = Low)........................................................ 3-2

3.1.3 Parallel Interface Configuration Only (PARIF = High)..................................................................................... 3-3

3.1.3.1 Parallel Host Bus Interface ......................................................................................................... 3-3

3.1.4 CX81801 Modem Interface Signals................................................................................................................ 3-3

3.2 CX20493 LSD Hardware Pins and Signals ................................................................................................................... 3-22

3.2.1 CX20493 LSD Signal Summary.................................................................................................................... 3-22

3.2.1.1 Smart Modem Interface (Through DIB) ................................................................................... 3-22

3.2.1.2 Telephone Line Interface .......................................................................................................... 3-22

3.2.1.3 Voltage References................................................................................................................... 3-22

3.2.1.4 General Purpose Input/Output.................................................................................................. 3-23

3.2.1.5 No Connects ............................................................................................................................. 3-23

3.2.2 CX20493 LSD Pin Assignments and Signal Definitions ............................................................................... 3-23

3.3 CX20442 VC Hardware Pins and Signals (S Models)................................................................................................... 3-28

3.3.1 CX20442 VC Signal Summary...................................................................................................................... 3-28

3.3.1.1 Speakerphone Interface............................................................................................................ 3-28

3.3.1.2 Telephone Handset/Headset Interface...................................................................................... 3-28

3.3.1.3 CX81801 Modem Interface....................................................................................................... 3-28

3.3.1.4 Host Interface........................................................................................................................... 3-28

3.3.2 CX20442 VC Pin Assignments and Signal Definitions ................................................................................. 3-29

3.4 Electrical and Environmental Specifications ................................................................................................................. 3-35

3.4.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements ........................................... 3-35

3.4.2 Interface and Timing Waveforms ................................................................................................................. 3-37

3.4.2.1 External Memory Bus Timing ................................................................................................... 3-37

3.4.2.2 Parallel Host Bus Timing .......................................................................................................... 3-39

3.4.2.3 Serial DTE Interface.................................................................................................................. 3-41

3.5 Crystal Specifications ................................................................................................................................................... 3-42

4. Package Dimensions ............................................................................................................................4-1

5. Parallel Host Interface ..........................................................................................................................5-1

5.1 Overview ......................................................................................................................................................................... 5-1

5.2 Register Signal Definitions ............................................................................................................................................. 5-3

5.2.1 IER - Interrupt Enable Register (Addr = 1, DLAB = 0) .................................................................................... 5-3

5.2.2 FCR - FIFO Control Register (Addr = 2, Write Only) ....................................................................................... 5-4

5.2.3 IIR - Interrupt Identifier Register (Addr = 2) .................................................................................................. 5-5

5.2.4 LCR - Line Control Register (Addr = 3) .......................................................................................................... 5-6

5.2.5 MCR - Modem Control Register (Addr = 4).................................................................................................... 5-7

5.2.6 LSR - Line Status Register (Addr = 5)............................................................................................................ 5-7

5.2.7 MSR - Modem Status Register (Addr = 6) ..................................................................................................... 5-9

5.2.8 RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0) ................................................................ 5-9

5.2.9 THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0).......................................................... 5-9

5.2.10 Divisor Registers (Addr = 0 and 1, DLAB = 1).............................................................................................. 5-10

5.3 Receiver FIFO Interrupt Operation ................................................................................................................................ 5-10

5.3.1 Receiver Data Available Interrupt ................................................................................................................. 5-10

5.3.2 Receiver Character Timeout Interrupts......................................................................................................... 5-11

5.4 Transmitter FIFO Interrupt Operation ........................................................................................................................... 5-11

5.4.1 Transmitter Empty Interrupt......................................................................................................................... 5-11

102199B

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