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PJ3842B

High Performance Current Mode Controller

Promax Johnton 

PJ3842B / PJ3843B

High Performance Current Mode Controller

Design Considerations

Do not attempt to construct the converter on wirewrap or

plug-in prototype boards. High frequency circuit layout

techniques are imperative to prevent pulsewidth jitter.This is

usually caused by excessive noise pick-up imposed on the

Current Sense or Voltage Feedback inputs.Noise immunity

can be improved by lowering circuit impedances at these

points.The printed circuit layout should contain a ground

plane with lowcurrent signal and high-current switch and

output grounds returning separate paths back to the input filter

capacitor.Ceramic bypass capacitors(0.1 μ F) connected

directly to Vcc,Vc, and Vref may be required depending upon

circuit layout . This provides a low impedance path for

filtering the high frequency noised. All high current loops

should be kept as short as possible using heavy copper runs to

minimize radiated EMI. The Error Amp compensation

circuitry and the converter output voltage divider should be

located close to the IC and as far as possible from the power

switch and other noise generating components.

FIGURE 19-CONTINUOUS CURRENT WAVEFROMS

Current mode converters can exhibit subharmonic

oscillations when operating at a duty cycle greater than 50%

with continuous inductor current,This instability is

independent of the regulators closed loop characteristics and

is caused by the simultaneous operating conditions of fixed

frequency and peak current detecting. Figure 19A shows the

phenomenon graphically, At t0 , switch conduction begins ,

causing the inductor current to rise at a slope of m1. This

slope is a function of the input voltage divided by the

inductance. At t1, the Current Sense Input reaches the

threshold established by the control voltage. This causes the

switch to turn off and the current to decay at a slope of m2,

until the next oscillator cycle. This unstable condition can be

shown if a perturbation is added to the control voltage ,

resulting in a small Δl (dashed line). With a fixed oscillator

period, the current decay time is reduced, and the minimum

current at switch turn-on(t2) is increased by Δl+Δl m2/m1.

The minimum current at the next cycle (t3) decreases to (Δl+

Δl m2/m1)(m2/m1). This perturbation is multiplied by m2/m1

on each succeeding cycle , alternately increasing and

decreasing the inductor current at switch turn-on, Several

oscillator cycles may be required before the inductor current

reaches zero causing the process to commence again. If m2/m1

is greater than 1, the converter will be unstable . Figure 19B

shows that by adding an artificial ramp that is synchronized

with the PWM clock to the control voltage . the Δ l

perturbation will decrease to zero on succeeding cycles. This

compensating ramp (m3) must have a slope equal to or slightly

greater than m2/2 for stability . With m2/2 slope

compensation , the average inductor current follows the

control voltage yielding true current mode operation. The

compensating ramp can be derived from the oscillator and

added to either the Voltage Feedback or Current Sense inputs

(Figure 32).

8-14

2004/11.Rev B

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