CDB5351(2002) Просмотр технического описания (PDF) - Cirrus Logic

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CDB5351
(Rev.:2002)

108 dB, 192 kHz, Multi-Bit Audio A/D Converter

Cirrus Logic 

CS5351

as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to

detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R

data will return to a logical high if there has not been any other overrange condition detected. Please note

that an overrange condition on either channel will restart the timeout period for both channels.

3.6.1 OVFL Output Timing

In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format,

the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both

cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified

format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of

LRCK would latch the left channel overflow status. In I2S format, the falling edge of LRCK would latch

the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.

3.7 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5351 requires careful attention to power supply and ground-

ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power

arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be

run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no

additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as

possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be

kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The

FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electri-

cal path from FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and

power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS

inputs.

3.8 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the sys-

tem. If only one master clock source is needed, one solution is to place one CS5351 in Master mode, and

slave all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible

solution would be to supply all clocks from the same external source and time the CS5351 reset with the

inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

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DS565PP2

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