CS5165 Просмотр технического описания (PDF) - ON Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CS5165

5−Bit Synchronous CPU Buck Controller

ON Semiconductor 

CS5165

ABSOLUTE MAXIMUM RATINGS

Pin Name

Pin Symbol

IC Power Input

VCC

Soft Start Capacitor

SS

Compensation Capacitor

COMP

Voltage Feedback Input

Off−Time Capacitor

Voltage ID DAC Inputs

High−Side FET Driver

VFB

COFF

VID0−VID4

GATE(H)

Low−Side FET Driver

GATE(L)

Enable Input

ENABLE

Power Good Output

PWRGD

Power Ground

PGND

Logic Ground

LGND

VMAX

16 V

6.0 V

6.0 V

6.0 V

6.0 V

6.0 V

16 V

16 V

6.0 V

6.0 V

0V

0V

VMIN

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

−0.3 V

0V

0V

ISOURCE

N/A

200 μA

10 mA

10 μA

1.0 mA

1.0 mA

1.5 A peak, 200 mA DC

1.5 A peak, 200 mA DC

100 μA

10 μA

1.5 A peak, 200 mA DC

100 mA

ISINK

1.5 A peak, 200 mA DC

10 μA

1.0 mA

10 μA

50 mA

10 μA

1.5 A peak, 200 mA DC

1.5 A peak, 200 mA DC

1.0 mA

30 mA

N/A

N/A

ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code:

(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

VCC Supply Current

Operating

1.0 V < VFB < VDAC (max on−time)

No Loads on GATE(H) and GATE(L)

−

12

20

mA

Sleep Mode

ENABLE = 0 V

−

300

600

μA

VCC Monitor

Start Threshold

GATE(H) switching

3.75

3.95

4.15

V

Stop Threshold

GATE(H) not switching

3.65

3.87

4.05

V

Hysteresis

Start−Stop

−

80

−

mV

Error Amplifier

VFB Bias Current

COMP Source Current

COMP CLAMP Voltage

VFB = 0 V

COMP = 1.2 V to 3.6 V; VFB = 2.7 V

VFB = 2.7 V, Adjust COMP voltage for Comp

current = 50 μA

−

0.1

1.0

μA

15

30

60

μA

0.85

1.0

1.15

V

COMP Clamp Current

COMP Sink Current

Open Loop Gain

COMP = 0 V

VCOMP = 1.2 V; VFB = 3.0 V; VSS > 2.5 V

Note 2

0.4

1.0

1.6

mA

180

400

800

μA

50

60

−

dB

Unity Gain Bandwidth

Note 2

0.5

2.0

−

MHz

PSRR @ 1.0 kHz

Note 2

60

85

−

dB

GATE(H) and GATE(L)

High Voltage at 100 mA

Low Voltage at 100 mA

Measure VCC − GATE

Measure GATE

−

1.2

2.0

V

−

1.0

1.5

V

Rise Time

Fall Time

GATE(H) to GATE(L) Delay

1.6 V < GATE < (VCC − 2.5 V)

(VCC − 2.5 V) > GATE > 1.6 V

GATE(H) < 2.0 V; GATE(L) > 2.0 V

−

40

80

ns

−

40

80

ns

30

65

100

ns

GATE(L) to GATE(H) Delay

GATE pull−down

GATE(L) < 2.0 V; GATE(H) > 2.0 V

Resistor to PGND, Note 2

30

65

100

ns

20

50

115

kΩ

2. Guaranteed by design, not 100% tested in production.

http://onsemi.com

3

Share Link: