CDB43L43 Просмотр технического описания (PDF) - Cirrus Logic

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CDB43L43

Low Voltage, Stereo DAC with Headphone Amp

Cirrus Logic 

CS43L43

3.0 APPLICATIONS

3.1 Sample Rate Range/Operational Mode Select

The device operates in one of two operational modes. Operation in either mode depends on the input sam-

ple rate and the ratio of the master clock to the left/right clock (see section 3.2). Sample rates outside the

specified range for each mode are not supported.

Input Sample Rate (FS)

2kHz - 50kHz

50kHz - 100kHz

MODE

Single Speed Mode

Double Speed Mode

Table 1. CS43L43 Operational Mode

3.2 System Clocking

The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device

also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The

LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to

specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates

and the required MCLK frequency, are illustrated in Tables 2-3.

Sample Rate

(kHz)

32

44.1

48

MCLK (MHz)

256x

8.1920

11.2896

12.2880

384x

12.2880

16.9344

18.4320

512x

16.3840

22.5792

24.5760

768x*

24.5760

33.8688

36.8640

Table 2. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

64

88.2

96

128x

8.1920

11.2896

12.2880

192x

12.2880

16.9344

18.4320

MCLK (MHz)

256x*

16.3840

22.5792

24.5760

Table 3. Double-Speed Mode Standard Frequencies

*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Bh).

1024x*

32.768

45.1584

49.1520

384x*

24.5760

33.8688

36.8640

6

DS479PP3

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