CMX615D4 Просмотр технического описания (PDF) - CML Microsystems Plc

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производитель

CMX615D4

Digital Line to POTS Interface

CML Microsystems Plc 

Digital Line to POTS Interface

CMX615

CMX615

D4/P3

Pin No.

11

12

13

14

15

16

Signal

Description

Name

VBIAS

OPPIN

OPNIN

OPOUT

RING

VDD

Type

O/P An internally generated bias voltage of VDD/2,

except when the device is in ‘Zero Power’ mode

when VBIAS will discharge to VSS. It should be

decoupled to VSS by a capacitor mounted close

to the device pins.

I/P The non-inverting input to the uncommitted

amplifier.

I/P The inverting input to the uncommitted amplifier.

O/P The output of the uncommitted amplifier.

O/P The squarewave output of the Ringing Signal

generator.

Power

The positive supply rail. Levels within the device

are proportional to this voltage. It should be

decoupled to VSS by a capacitor mounted close

to the device pins.

Notes:

I/P

= Input

O/P = Output

T/S = 3-state Output

It is recommended that the printed circuit board is laid out with a ground plane in the CMX615 area

to provide a low impedance connection between the VSS pin and the VDD and VBIAS decoupling

capacitors.

© 1999 Consumer Microcircuits Limited

5

D/615/4

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