CM2030
Table 1. PIN DESCRIPTIONS
Pins
Name
ESD Level
Description
4, 35
TMDS_D2+
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
6, 33
TMDS_D2−
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
7, 32
TMDS_D1+
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
9, 30
TMDS_D1−
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
10, 29
TMDS_D0+
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
12, 27
TMDS_D0−
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
13, 26
TMDS_CK+
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
15, 24
TMDS_CK−
8 kV (Note 3) TMDS 0.9 pF ESD Protection (Note 1)
16
CE_REMOTE_IN 2 kV (Note 4) CE_SUPPLY Referenced Logic Level In
23
CE_REMOTE_OUT 8 kV(Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
17
DDC_CLK_IN
2 kV (Note 4) LV_SUPPLY Referenced Logic Level In
22
DDC_CLK_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
18
DDC_DAT_IN
2 kV (Note 4) LV_SUPPLY Referenced Logic Level In
21
DDC_DAT_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
19
HOTPLUG_DET_IN 2 kV (Note 4) LV_SUPPLY Referenced Logic Level In
20
HOTPLUG_DET_OUT 8 kV (Note 3) 5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD. A 0.1 mF Bypass
Ceramic Capacitor is Recommended on this Pin (Note 2).
2
LV_SUPPLY
2 kV (Note 4) Bias for CE / DDC / HOTPLUG Level Shifters
37
CE_SUPPLY
2 kV
CEC Bias Voltage. Previously CM2020 ESD_BYP Pin.
(Notes 2 & 4)
1
5V_SUPPLY
2 kV (Note 4) Current Source for 5V_OUT, VREF for DDC I2C Voltage References, and Bias for
8 kV ESD Pins.
38
5V_OUT
8 kV (Note 3) 55 mA Minimum Overcurrent Protected 5 V Output. This Output Must be
Bypassed with a 0.1 mF Ceramic Capacitor.
3, 5, 8, 11,
14, 25, 28,
31, 34, 36
GND / TMDS_GND
N/A
GND Reference
1. These 2 pins need to be connected together in−line on the PCB. See recommended layout diagram.
2. This output can be connected to an external 0.1 mF ceramic capacitor/pads to maintain backward compatibility with the CM2020.
3. Standard IEC 61000−4−2, CDISCHARGE = 150 pF, RDISCHARGE = 330 W, 5V_SUPPLY and LV_SUPPLY within recommended operating
conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 mF ceramic capacitor connected
to GND.
4. Human Body Model per MIL−STD−883, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kW, 5V_SUPPLY and LV_SUPPLY within
recommended operating conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 mF ceramic
capacitor connected to GND.
5. These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector.
6. The slew−rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins.
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