CDP1802A Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

CDP1802A

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

INSTRUCTION

RESET Q

SAVE

PUSH X, P TO STACK

RETURN

DISABLE

INPUT - OUTPUT BYTE TRANSFER

OUTPUT 1

OUTPUT 2

OUTPUT 3

OUTPUT 4

OUTPUT 5

OUTPUT 6

OUTPUT 7

INPUT 1

INPUT 2

INPUT 3

INPUT 4

INPUT 5

INPUT 6

INPUT 7

MNEMONIC

REQ

SAV

MARK

RET

DlS

OP

CODE

7A

78

79

70

71

OPERATION

0→Q

T → M(R(X))

(X, P) → T; (X, P) → M(R(2)), THEN P → X; R(2) - 1 → R(2)

M(R(X)) → (X, P); R(X) + 1 → R(X), 1 → lE

M(R(X)) → (X, P); R(X) + 1 → R(X), 0 → lE

OUT 1

OUT 2

OUT 3

OUT 4

OUT 5

OUT 6

OUT 7

INP 1

INP 2

INP 3

INP 4

INP 5

INP 6

INP 7

61 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 1

62 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 2

63 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 3

64 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 4

65 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 5

66 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 6

67 M(R(X)) → BUS; R(X) + 1 → R(X); N LINES = 7

69 BUS → M(R(X)); BUS → D; N LINES = 1

6A BUS → M(R(X)); BUS → D; N LINES = 2

6B BUS → M(R(X)); BUS → D; N LINES = 3

6C BUS → M(R(X)); BUS → D; N LINES = 4

6D BUS → M(R(X)); BUS → D; N LINES = 5

6E BUS → M(R(X)); BUS → D; N LINES = 6

6F BUS → M(R(X)); BUS → D; N LINES = 7

3-26

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