CDP1802AC/3 Просмотр технического описания (PDF) - Intersil

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CDP1802AC/3

High-Reliability CMOS 8-Bit Microprocessor

Intersil 

CDP1802AC/3

Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

-55°C TO +25°C

+125°C

PARAMETERS

PROGAGATION DELAY TIMES, tPLH, tPHL

Clock to TPA, TPB

VDD (V)

MIN

5

-

MAX

275

MIN

MAX

UNITS

-

370

ns

Clock-to-Memory High Address Byte, tPLH, tPHL

Clock-to-Memory Low Address Byte Valid, tPLH, tPHL

Clock to MRD, tPLH, tPHL

Clock to MWR, tPLH, tPHL

Clock to (CPU DATA to BUS) Valid, tPLH, tPHL

Clock to State Code, tPLH, tPHL

Clock to Q, tPLH, tPHL

Clock to N (0 to 2), tPLH, tPHL

INTERFACE TIMING REQUIREMENTS (Note 7)

5

-

725

-

950

ns

5

-

340

-

425

ns

5

-

340

-

425

ns

5

-

275

-

370

ns

5

-

430

-

550

ns

5

-

440

-

550

ns

5

-

375

-

475

ns

5

-

400

-

525

ns

Data Bus Input Setup, tSU

Data Bus Input Hold, tH

DMA Setup, tSU

DMA Hold, tH

Interrupt Setup, tSU

Interrupt Hold, tH

WAIT Setup, tSU

EF1-4 Setup, tSU

EF1-4 Hold, tH

REQUIRED PULSE WIDTH TIMES

5

10

-

10

-

ns

5

175

-

230

-

ns

5

10

-

10

-

ns

5

200

-

270

-

ns

5

10

-

10

-

ns

5

175

-

230

-

ns

5

30

-

30

-

ns

5

20

-

20

-

ns

5

100

-

135

-

ns

CLEAR Pulse Width, tWL

5

CLOCK Pulse Width, tWL

5

NOTE:

7. Minimum input setup and hold times required by Part CDP1802AC/3.

150

-

200

-

ns

140

-

185

-

ns

FN1441 Rev 3.00

October 17, 2008

Page 6 of 27

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