CAT5172(2009) Просмотр технического описания (PDF) - ON Semiconductor
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CAT5172 Datasheet PDF : 10 Pages
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CAT5172
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
VDD = 5 V ±10%, or 3 V ±10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Typ
Min
(Note 2) Max
Unit
DC CHARACTERISTICS — RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 3)
RWB, VA = no connection
R−DNL
−1
Resistor Integral Nonlinearity (Note 3)
RWB, VA = no connection
R−INL
−2
Nominal Resistor Tolerance (Note 4)
TA = 25°C
nRAB
−20
Resistance Temperature Coefficient
VAB = VDD, Wiper = no connection nRAB/nT
Wiper Resistance
VDD = 5 V
RW
VDD = 3 V
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE
±0.1
+1
LSB
±0.4
+2
LSB
+20
%
100
ppm/°C
50
120
W
100
250
Resolution
N
8
Bits
Differential Nonlinearity (Note 5)
DNL
−1
±0.1
+1
LSB
Integral Nonlinearity (Note 5)
INL
−1
±0.4
+1
LSB
Voltage Divider Temperature Coefficient
Full−Scale Error
Zero−Scale Error
RESISTOR TERMINALS
Code = 0x80
Code = 0xFF
Code = 0x00
nVW/nT
VWFSE
−3
VWZSE
0
100
ppm/°C
−1
0
LSB
1
3
LSB
Voltage Range (Note 6)
Capacitance (Note 7) A, B
f = 1 MHz, measured to GND,
Code = 0 x 80
VA,B,W
CA,B
GND
VDD
V
45
pF
Capacitance (Note 7) W
f = 1 MHz, measured to GND,
CW
Code = 0 x 80
60
pF
Common−Mode Leakage (Note 7)
DIGITAL INPUTS
VA = VB = VDD/2
ICM
1
nA
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance (Note 7)
POWER SUPPLIES
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
VIH
0.7 x VDD
V
VIL
0.3VDD
V
VIH
0.7 x VDD
V
VIL
0.3VDD
V
IIL
±1
mA
CIL
5
pF
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
VIH = 5 V or VIL = 0 V
IDD
0.3
2
mA
Power Dissipation (Note 8)
VIH = 5 V or VIL = 0 V, VDD = 5 V
PDISS
0.2
mW
Power Supply Sensitivity
nVDD = +5 V ±10%, Code = Midscale PSS
±0.05 %/%
2. Typical specifications represent average readings at +25°C and VDD = 5 V.
3. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minim-
um resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaran-
teed monotonic.
4. VAB = VDD, Wiper (VW) = no connect.
5. INL and DNL are measured at VW with the DPP configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD
and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
7. Guaranteed by design and not subject to production test.
8. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
9. All dynamic characteristics use VDD = 5 V.
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