CAT28LV65 Просмотр технического описания (PDF) - ON Semiconductor

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CAT28LV65

64 kb CMOS Parallel EEPROM

ON Semiconductor 

CAT28LV65

DEVICE OPERATION

Read

Data stored in the CAT28LV65 is transferred to the data

bus when WE is held high, and both OE and CE are held low.

The data bus is set to a high impedance state when either CE

or OE goes high. This 2−line control architecture can be used

to eliminate bus contention in a system environment.

Byte Write

A write cycle is executed when both CE and WE are low,

and OE is high. Write cycles can be initiated using either WE

or CE, with the address input being latched on the falling

edge of WE or CE, whichever occurs last. Data, conversely,

is latched on the rising edge of WE or CE, whichever occurs

first. Once initiated, a byte write cycle automatically erases

the addressed byte and the new data is written within 5 ms.

tRC

ADDRESS

tCE

CE

OE

WE

DATA OUT

tOE

VIH

tOLZ

tLZ

HIGH−Z

tAA

tOH

DATA VALID

tOHZ

tHZ

DATA VALID

Figure 4. Read Cycle

ADDRESS

CE

tAS

tAH

tCS

tWC

tCH

OE

WE

RDY/BUSY

DATA OUT

tOES

HIGH−Z

tWP

tRB

tOEH

tBLC

HIGH−Z

HIGH−Z

DATA IN

DATA VALID

tDS

tDH

Figure 5. Byte Write Cycle [WE Controlled]

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