CAT24C21YI-TE13 Просмотр технического описания (PDF) - Catalyst Semiconductor => Onsemi

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CAT24C21YI-TE13

1-kb Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"

Catalyst Semiconductor => Onsemi 

CAT24C21

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge (ACK). The

acknowledging device pulls down the SDA line during the

ninth clock cycle, signaling that it has received the 8 bits of

data (Figure 7).

The CAT24C21 responds with an ACK after receiving a

START condition and its slave address. If the device has

been selected along with a write operation, it responds

with an ACK after receiving each 8-bit byte.

When the CAT24C21 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the line

for an ACK. Once it receives this ACK, the CAT24C21

will continue to transmit data. If no ACK is sent by the

Master, the device terminates data transmission and

waits for a STOP condition.

Write Operations

VCLK must be held high in order to program the device.

This applies to byte write and page write operation.

Once the device is in its self-timed program cycle,

VCLK can go low and not affect programming.

Byte Write

In the Byte Write mode (Figure 9), the Master device

sends the START condition and the slave address

information (with the R/W bit set to zero) to the Slave

device. After the Slave generates an ACK, the Master

sends the byte address that is to be written into the

address pointer of the CAT24C21. After receiving another

ACK from the Slave, the Master device transmits the

data byte to be written into the addressed memory

location. The CAT24C21 acknowledges once more and

the Master generates the STOP condition, at which time

the device begins its internal programming cycle to

nonvolatile memory (Figure 5). While this internal cycle

is in progress, the device will not respond to any request

from the Master device.

Figure 4. Bus Timing

tF

tHIGH

tR

tLOW

tLOW

SCL

tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

SDA IN

SDA OUT

tAA

tDH

tSU:STO

tBUF

Figure 5. Write Cycle Timing

SCL

SDA

8th Bit

Byte n

ACK

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

Doc. No. 1032, Rev. O

6

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