CAT24C21YI-TE13 Просмотр технического описания (PDF) - Catalyst Semiconductor => Onsemi

Номер в каталоге

Компоненты Описание

производитель

CAT24C21YI-TE13

1-kb Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"

Catalyst Semiconductor => Onsemi 

CAT24C21

BI-DIRECTIONAL MODE (DDC2)

The following defines the features of the I2C bus protocol

in bi-directional mode (Figure 4):

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

When in the bi-directional mode, all inputs to the VCLK

pin are ignored, except when a logic high is required to

enable write capability.

START Condition

The START condition (Figure 6) precedes all commands

to the device, and is defined as a HIGH to LOW transition

of SDA when SCL is HIGH. The CAT24C21 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are fixed

as 1010 for the CAT24C21 (see Fig. 8). The next three

significant bits are "don't care". The last bit of the slave

address specifies whether a Read or Write operation is

to be performed. When this bit is set to 1, a Read

operation is selected, and when set to 0, a Write operation

is selected.

After the Master sends a START condition and the slave

address byte, the CAT24C21 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24C21 then performs a Read or Write operation

depending on the state of the R/W bit.

Figure 3. Transmit-only Mode

SCL must remain high for transmit-only mode

SCL

SDA

VCLK

Bit8

(MSB)

Bit7

Bit6

Bit5

Bit4 Bit3

Bit2

Bit1

(LSB)

Don't

Care

Bit8

Bit7

TVHIGH

TVLOW

5

Doc. No. 1032, Rev. O

Share Link: