CAT24C208 Просмотр технического описания (PDF) - Catalyst Semiconductor => Onsemi
Номер в каталоге
Компоненты Описание
производитель
CAT24C208 Datasheet PDF : 13 Pages
| |||
CAT24C208
DEVICE ADDRESSING
DDC Interface
Both the DDC and DSP interfaces to the device are
based on the I2C bus serial interface. All memory space
operations are done at the A0/A1 DDC address pair. As
such, all write operations to the memory space are done
at DDC address A0h and all read operations of the
memory space are done at DDC address A1h.
Figure 3 shows the bit sequence of a random read from
anywhere within the memory space. The word offset
determines which of the 256 bytes within segment 00h
is being read. Here the segment 00h can be at the lower
or upper bank depending on the configuration register.
Sequential reads can be done in much the same manner
by reading successive bytes after each acknowledge
without generating a stop condition. See Figure 4. The
device automatically increments the word offset value
(8-bit value) and with wraparound in the same segment
00h to read maximum of 256 bytes.
Figure 3. Random Access Read (Segment 00h only)
WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK START 1010 0001 ACK DATA NOACK STOP
Figure 4. Sequential Read (Segment 00h only)
WORD OFFSET
START
1010 0000
ACK
A7 - A0
ADDRESS
ACK
START
1010 0001 ACK
DATA0
ACK
......... DATAN NOACK STOP
Figures 5 and 6 show the byte and page write respectively. The configuration register must have the WE bit set to 1
prior to any write on DDC Port. Only the segment 00h can be accessed of either lower or upper bank.
Figure 5. Byte Write (Segment 00h only)
WORD OFFSET
START 1010 0000
ACK
A7 - A0 ADDRESS
ACK
DATA
ACK
STOP
Figure 6. Page Write (Segment 00h only)
WORD OFFSET
START 1010 0000 ACK A7 - A0 ADDRESS ACK
DATA0
ACK
......... DATA15 ACK STOP
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1044, Rev. F
Share Link: 