CAT24AA01 Просмотр технического описания (PDF) - Catalyst Semiconductor => Onsemi

Номер в каталоге

Компоненты Описание

производитель

CAT24AA01

1-Kb and 2-Kb I2C CMOS Serial EEPROM

Catalyst Semiconductor => Onsemi 

CAT24AA01, CAT24AA02

POWER-ON RESET (POR)

Each CAT24AA01/02 incorporates Power-On Reset

(POR) circuitry which protects the internal logic

against powering up in the wrong state. The device

will power up into Standby mode after VCC exceeds

the POR trigger level and will power down into Reset

mode when VCC drops below the POR trigger level.

This bi-directional POR behavior protects the

device against brown-out failure, following a

temporary loss of power.

PIN DESCRIPTION

SCL: The Serial Clock input pin accepts the clock

signal generated by the Master.

SDA: The Serial Data I/O pin accepts input data and

delivers output data. In transmit mode, this pin is open

drain. Data is acquired on the positive edge, and

delivered on the negative edge of SCL.

WP: When the Write Protect input pin is forced HIGH

by an external source, all write operations are

inhibited. When the pin is not driven by an external

source, it is pulled LOW internally.

FUNCTIONAL DESCRIPTION

The CAT24AA01/02 supports the Inter-Integrated

Circuit (I2C) Bus protocol. The protocol relies on the

use of a Master device, which provides the clock and

directs bus traffic, and Slave devices which execute

requests. The CAT24AA01/02 operates as a Slave

device. Both Master and Slave can transmit or

receive, but only the Master can assign those roles.

I2C BUS PROTOCOL

The 2-wire I2C bus consists of two lines, SCL and

SDA, connected to the VCC supply via pull-up

resistors. The Master provides the clock to the SCL

line, and the Master and Slaves drive the SDA line. A

‘0’ is transmitted by pulling a line LOW and a ‘1’ by

releasing it HIGH. Data transfer may be initiated only

when the bus is not busy (see A.C. Characteristics).

During data transfer, SDA must remain stable while

SCL is HIGH.

START/STOP Condition

An SDA transition while SCL is HIGH creates a

START or STOP condition (Figure 1). A START is

generated by a HIGH to LOW transition, while a

STOP is generated by a LOW to HIGH transition. The

START acts like a wake-up call. Absent a START, no

Slave will respond to the Master. The STOP

completes all commands.

Device Addressing

The Master addresses a Slave by creating a START

condition and then broadcasting an 8-bit Slave

address (Figure 2). The first four bits of the Slave

address are 1010 (Ah).

For the CAT24AA01/02 the next three bits must

be 000.

The last bit, R/¯W¯, instructs the Slave to either provide

(1) or accept (0) data, i.e. it signals a Read (1) or a

Write (0) request.

Acknowledge

During the 9th clock cycle following every byte sent

onto the bus, the transmitter releases the SDA line,

allowing the receiver to respond. The receiver then

either acknowledges (ACK) by pulling SDA LOW, or

does not acknowledge (NoACK) by letting SDA stay

HIGH (Figure 3). Bus timing is illustrated in Figure 4.

Doc. No. MD-1120 Rev. B

4

© Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Share Link: