Figure 1. START/STOP Conditions
CAT24C01/02/04/08/16
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0 A2 A1 A0 R/W CAT24C01 and CAT24C02
1
0
1
0 A2 A1 a8 R/W CAT24C04
1
0
1
0 A2 a9 a8 R/W CAT24C08
1
0
1
0 a10 a9 a8 R/W CAT24C16
Figure 3. Acknowledge Timing
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (≥ tSU:DAT)
Figure 4. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1115, Rev. C