CAT1021LI-25-G(2009) Просмотр технического описания (PDF) - ON Semiconductor

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CAT1021LI-25-G
(Rev.:2009)

Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer

ON Semiconductor 

CAT1021, CAT1022, CAT1023

RESET CIRCUIT AC CHARACTERISTICS

Symbol

tPURST

tRDP

tGLITCH

MR Glitch

tMRW

tMRD

tWD

Parameter

Power-Up Reset Timeout

VTH to RESET output Delay

VCC Glitch Reject Pulse Width

Manual Reset Glitch Immunity

MR Pulse Width

MR Input to RESET Output Delay

Watchdog Timeout

POWER-UP TIMING (5), (6)

Symbol

tPUR

tPUW

Parameter

Power-Up to Read Operation

Power-Up to Write Operation

Test Conditions Min Typ

Note 2

130 200

Note 3

Note 4, 5

Note 1

Note 1

5

Note 1

Note 1

1.0

1.6

Max

270

5

30

100

1

2.1

Units

ms

µs

ns

ns

µs

µs

sec

Test Conditions Min Typ Max Units

270

ms

270

ms

AC TEST CONDITIONS

Parameter

Input Pulse Voltages

Input Rise and Fall times

Input Reference Voltages

Output Reference Voltages

Output Load

Test Conditions

0.2 x VCC to 0.8 x VCC

10 ns

0.3 x VCC , 0.7 x VCC

0.5 x VCC

Current Source: IOL = 3 mA; CL = 100 pF

RELIABILITY CHARACTERISTICS

Symbol

NEND(5)

TDR(5)

VZAP(5)

ILTH(5)(7)

Parameter

Endurance

Data Retention

ESD Susceptibility

Latch-Up

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

2000

100

Max

Units

Cycles/Byte

Years

Volts

mA

Notes:

(1) Test Conditions according to “AC Test Conditions” table.

(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data

(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.

(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.

Doc. No. MD-3009 Rev. P

6

© 2009 SCILLC. All rights reserved.

Characteristics subject to change without notice

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