ACX306AK Просмотр технического описания (PDF) - Sony Semiconductor
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ACX306AK Datasheet PDF : 23 Pages
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ACX306AK
2. Panel input signal voltage conditions
(VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
(Low)
VIL
H/V driver input voltage
(High) VIH
–0.3
0.0
2.6
3.0
0.3
V
5.5
V
REF input voltage
Video signal center voltage∗4
VREF
VVC
VIH/2 – 0.3
5.8
VIH/2
6.0
VIH/2 + 0.3
V
6.2
V
Video signal input range∗4
Uniformity improvement signal∗4
Vsig
Vpsig
1.0
VVC ± 4.0
VDDG – 4.0
(10.5V or less)
V
VVC ± 2.3 VVC ± 2.5 VVC ± 2.7
V
Common voltage of panel (Ta = 25°C) Vcom
VVC – 0.6 VVC – 0.5 VVC – 0.4
V
∗4 Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC
as shown in Fig. 1.
PSIG waveform
VVC
Vpsig
Fig. 1
Pin Description of Panel Block
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1 TESTL Panel test output; no connection
13 HST
Start pulse input for H shift register
drive
2 COM Common voltage input of panel
14 REF
Level shifter circuit REF voltage
input
3 VST
Start pulse input for V shift register
drive
15 TEST
Panel test output; no connection
4 VCK
Clock input for V shift register drive
16
Cext/
Rext
Time constant power supply input
for H shift register drive
5 EN
Gate selection pulse enable input 17 HCK2 Clock input for H shift register drive
6
DWN
V shift register drive direction signal
input
18
HCK1
Clock input for H shift register drive
7 VDD
Power supply input for V driver
19 PSIG Uniformity improvement signal input
8 VSS
H and V driver GND
20 GREEN Video signal (G) input to panel
9
VDDG
Boost power supply setting for
V driver
21 RED Video signal (R) input to panel
10
VSSG
Negative power supply setting for
V driver
22 BLUE Video signal (B) input to panel
11
TEST2
No connection inside the panel.
(with 1MΩ terminating resistor)
23 RGT
H shift register drive direction signal
input
12 WIDE
Uniformity improvement signal
control pulse input
24
–4–
TESTR Panel test output; no connection
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