CA3094 Просмотр технического описания (PDF) - Intersil
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CA3094 Datasheet PDF : 14 Pages
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CA3094, CA3094A, CA3094B
Operating Considerations
The “Sink” Output (Terminal 8) and the “Drive” Output
(Terminal 6) of the CA3094 are not inherently current (or
power) limited. Therefore, if a load is connected between
Terminal 6 and Terminal 4 (V- or Ground), it is important to
connect a current limiting resistor between Terminal 8 and
Terminal 7 (V+) to protect transistor Q13 under shorted load
conditions. Similarly, if a load is connected between
Terminal 8 and Terminal 7 (V+), the current limiting resistor
should be connected between Terminal 6 and Terminal 4 or
ground. In circuit applications where the emitter of the output
transistor is not connected to the most negative potential in
the system, it is recommended that a 100Ω current limiting
resistor be inserted between Terminal 7 and the V+ supply.
1/F Noise Measurement Circuit
When using the CA3094, A, or B audio amplifier circuits, it is
frequently necessary to consider the noise performance of the
device. Noise measurements are made in the circuit shown in
Figure 20. This circuit is a 30dB, non-inverting amplifier with
emitter follower output and phase compensation from
Terminal 2 to ground. Source resistors (RS) are set to 0Ω or
1MΩ for E noise and I noise measurements, respectively.
These measurements are made at frequencies of 10Hz,
100Hz and 1kHz with a 1Hz measurement bandwidth. Typical
values for 1/f noise at 10Hz and 50µA IABC are:
EN = 18nV ⁄ Hz and IN = 1.8pA ⁄ Hz .
Test Circuits
2
100Ω
3
100Ω
15V
30V
7
300kΩ
5
9.9kΩ
CA3094
6
1
8
4
10kΩ
1kΩ
100pF
EOUT
30V
NOTES:
3. Input Offset Voltage:
VIO
=
E----1-O---0--U-0----T-- .
4. For Power Supply Rejection Test: (1) vary V+ by -2V; then (2)
vary V- by +2V.
5. Equations:
(1) V+ Rejection = E----0----O------U----T--2---0-–---0-E----1----O-----U-----T--
(2) V- Rejection = E-----0----O-----U-----T-2----0–---0-E----2----O-----U-----T--
6. Power Supply Rejection: (d B) = 20log -V----R-----E----J---E-----C1----T-----I--O-----N-----†-- .
† Maximum Reading of Step 1 or Step 2
FIGURE 1. INPUT OFFSET VOLTAGE AND POWER SUPPLY REJECTION TEST CIRCUIT
30V
2
3
1MΩ
7
RABC
5
8
CA3094
6
1
150kΩ
4
220Ω
0.001µF
1MΩ
EOUT
15V
30V
7
300kΩ
5
2
-
CA3094A
15V
3
+
4
NOTES:
7. PDISSIPATION = (V+)(I)
8. IO S = 1----0----6E---V--O--A------O---U-M------L--T--P----T------S--S----
FIGURE 2. INPUT OFFSET CURRENT TEST CIRCUIT
NOTE: II = 2-I-
FIGURE 3. INPUT BIAS CURRENT TEST CIRCUIT
3-4
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