CA3094 Просмотр технического описания (PDF) - Intersil
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CA3094 Datasheet PDF : 14 Pages
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CA3094, CA3094A, CA3094B
Electrical Specifications TA = 25oC for Equipment Design. Single Supply V+ = 30V, Dual Supply VSUPPLY = ±15V, IABC = 100µA Unless
Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
OUTPUT PARAMETERS (Differential Input Voltage = 1V)
Peak Output Voltage With Q13 “ON”
(Terminal 6)
With Q13 “OFF”
VOM+
VOM-
V+ = 30V, RL = 2kΩ to GND
26
27
-
V
-
0.01
0.05
V
Peak Output Voltage Positive
(Terminal 6)
Negative
VOM+ V+ = 15V, V- = -15V, RL = 2kΩ to -15V
11
12
-
V
VOM-
-
-14.99 -14.95
V
Peak Output Voltage With Q13 “OFF”
(Terminal 8)
With Q13 “ON”
VOM+
VOM-
V+ = 30V, RL = 2kΩ to 30V
29.95 29.99
-
V
-
0.040
-
V
Peak Output Voltage Positive
(Terminal 8)
Negative
VOM+
VOM-
V+ = 15V, V- = -15V,
RL = 2kΩ to 15V
14.95 14.99
-
V
-
-14.96
-
V
Collector-to-Emitter Saturation Voltage
(Terminal 8)
VCE(SAT) V+ = 30V, IC = 50mA, Terminal 6
Grounded
-
0.17
0.80
V
Output Leakage Current
(Terminal 6 to Terminal 4)
V+ = 30V
-
2
10
µA
Composite Small Signal Current Transfer
Ratio (Beta) (Q12 and Q13)
hFE
V+ = 30V, VCE = 5V, IC = 50mA
16,000 100,000
-
Output Capacitance
Terminal 6
Terminal 8
CO
f = 1MHz, All Remaining Terminals Tied
-
5.5
-
pF
to Terminal 4
-
17
-
pF
TRANSFER PARAMETERS
Voltage Gain
A
V+ = 30V, IABC = 100µA, ∆VOUT = 20V, 20,000 100,000
-
V/V
RL = 2kΩ
86
100
-
dB
Forward Transconductance to
gM
Terminal 1
1650 2200 2750
µS
Slew Rate (Open
Loop)
Positive Slope
Negative Slope
Unity Gain (Non-Inverting Compensated)
SR
IABC = 500µA, RL = 2kΩ
IABC = 500µA, RL = 2kΩ
-
500
-
-
50
-
-
0.70
-
V/µs
V/µs
V/µs
Schematic Diagram
EXTERNAL FREQUENCY 1
COMPENSATION OR INHIBIT INPUT
7 V+
D3
Q4
Q7
Q6
D2
Q5
DIFFERENTIAL
VOLTAGE 2
INPUT
DIFFERENTIAL
VOLTAGE
INPUT
AMPLIFIER
BIAS INPUT 5
IABC
Q1
3
D1
Q2
Q3
D5
D4
R1
2kΩ
Q8
Q9
Q11
8
“SINK”
Q12 OUTPUT
Q10
R2
47kΩ
D6
4 V-
Q13
6
“SOURCE”
(DRIVE)
OUTPUT
OUTPUT OUTPUT
MODE TERM
“Source”
6
“Sink”
8
INPUTS
NON-
INV
INV
2
3
3
2
3-3
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