C9827H Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

C9827H

High Performance Pentium® 4 Clock Synthesizer

Cypress Semiconductor 

Approved Product

C9827H

High Performance Pentium® 4 Clock Synthesizer

Serial Control Registers (Cont.)

Byte 0: CPU Clock Register

Bit

@Pup

Pin#

Description

7

0

-

Spread Spectrum Enable

0 = Spread Off, 1 = Spread On

This is a Read and Write control bit.

6

0

-

Reserved

5

0

35

3V66_1/VCH frequency Select

0 = 66M selected, 1 = 48M selected

This is a Read and Write control bit.

4

Pin 53

44,45,48,49, CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.

51,52

3

Pin 34

10,11,12,13, Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a

16,17,18 logical AND function of the internal SMBus register bit and the external PCI_STP# pin.

2

Pin 40

-

Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.

1

Pin 55

-

Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.

0

Pin 54

-

Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.

Byte 1: CPU Clock Register

Bit

@Pup

7

Pin 43

6

0

5

0

4

0

3

0

2

1

1

1

0

1

Pin#

-

-

44,45

48,49

51,52

44,45

48,49

51,52

Description

MULT0 (Pin 43) Value. This bit is Read Only.

Reserved

Controls CPU2 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

Controls CPU1 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

Controls CPU0 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW

This is a Read and Write control bit.

CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW

This is a Read and Write control bit.

CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW

This is a Read and Write control bit.

Byte 2: PCI Clock Control Register

(all bits are read and write functional)

Byte 3: PCI_F Clock and 48M Control Register

(all bits are read and write functional)

Bit @Pup

7

0

6

1

5

1

4

1

3

1

2

1

1

1

0

1

Pin#

-

18

17

16

13

12

11

10

Description

Reserved

PCI6 Output Control

1 = enabled, 0 = forced LOW

PCI5 Output Control

1 = enabled, 0 = forced LOW

PCI4 Output Control

1 = enabled, 0 = forced LOW

PCI3 Output Control

1 = enabled, 0 = forced LOW

PCI2 Output Control

1 = enabled, 0 = forced LOW

PCI1 Output Control

1 = enabled, 0 = forced LOW

PCI0 Output Control

1 = enabled, 0 = forced LOW

Bit @Pup Pin# Description

7

1

38 48MDOT Output Control

1 = enabled, 0 = forced LOW

6

1

39 48MUSB Output Control

1 = enabled, 0 = forced LOW

5

0

7 PCI_STP#, control of PCI_F2.

0 = Free Running, 1 = Stopped when

PCI_STP# is LOW

4

0

6 PCI_STP#, control of PCI_F1.

0 = Free Running, 1 = Stopped when

PCI_STP# is LOW

3

0

5 PCI_STP#, control of PCI_F0.

0 = Free Running, 1 = Stopped when

PCI_STP# is LOW

2

1

7 PCI_F2 Output Control

1=running, 0=forced LOW

1

1

6 PCI_F1 Output Control

1= running, 0=forced LOW

0

1

5 PCI_F0 Output Control

1= running, 0=forced LOW

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07106 Rev. *A

12/26/2002

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