Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Maximum Lumped Capacitive Output
Loads
Clock
Max Load
PCI Clocks
30
3V66 (0,1)
30
66B(0:2)
30
48MUSB Clock
20
48MDOT
10
REF Clock
30
Table 5
Units
pF
pF
pF
pF
pF
pF
Maximum Ratings¹
Input Voltage Relative to VSS:
VSS-0.3V
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
Storage Temperature:
-65°C to + 150°C
Operating Temperature:
0°C to +85°C
Maximum Power Supply:
3.5V
Note 1: The voltage on any input or I/o pin cannot exceed the
power pin during power-up. Power supply sequencing is NOT
required.
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK
RtA1
Mult0
CLK#
RtA2
Rref
TPCB
RLA1
TPCB
RLA2
RLB1
RLB2
RtB1
RD
RtB2
CLK Measurement Point
CLA
CLK Measurement Point
CLB
Lumped Test Load Configuration
Component
RtA1, RtA2
RLA1, RLA2
TPCB
RLB1, RLB2
RD
RtB1, RtB2
CLA, CLB
Rref
0.7 Volt Amplitude Value
33 Ω
49.9 Ω
3” 50 ΩZ
∞
∞
0Ω
2pF
475 Ω w/mult0=1
Cypress Semiconductor Corporation
http://www.cypress.com
1.0 Volt Amplitude Value
0Ω
∞
3” 50 ΩZ
63 Ω
470 Ω
33 Ω
2 pF
221 Ω w/mult0=0
Document#: 38-07106 Rev. *A
12/26/2002
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