C8051F380 Просмотр технического описания (PDF) - Silicon Laboratories

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C8051F380

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

List of Figures

Figure 1.1. C8051F380/2/4/6 Block Diagram .......................................................... 18

Figure 1.2. C8051F381/3/5/7/C Block Diagram ....................................................... 19

Figure 3.1. TQFP-48 Pinout Diagram (Top View) ................................................... 25

Figure 3.2. TQFP-48 Package Diagram .................................................................. 26

Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 27

Figure 3.4. LQFP-32 Pinout Diagram (Top View) .................................................... 28

Figure 3.5. LQFP-32 Package Diagram .................................................................. 29

Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 30

Figure 3.7. QFN-32 Pinout Diagram (Top View) ..................................................... 31

Figure 3.8. QFN-32 Package Drawing .................................................................... 32

Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 33

Figure 4.1. Connection Diagram with Voltage Regulator Used and No USB .......... 34

Figure 4.2. Connection Diagram with Voltage Regulator Not Used and No USB ... 34

Figure 4.3. Connection Diagram with Voltage Regulator Used and USB Connected

(Bus-Powered) ................................................................................................... 35

Figure 4.4. Connection Diagram with Voltage Regulator Used and USB Connected

(Self-Powered) ................................................................................................... 35

Figure 4.5. Connection Diagram for USB Pins ........................................................ 36

Figure 4.6. Connection Diagram for Internal Voltage Reference ............................. 36

Figure 6.1. ADC0 Functional Block Diagram ........................................................... 46

Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 48

Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 49

Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 51

Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 52

Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 58

Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 58

Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 62

Figure 8.1. Comparator0 Functional Block Diagram ............................................... 64

Figure 8.2. Comparator1 Functional Block Diagram ............................................... 65

Figure 8.3. Comparator Hysteresis Plot .................................................................. 66

Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 71

Figure 11.1. CIP-51 Block Diagram ......................................................................... 79

Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F380/1/4/5) ............. 89

Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F382/3/6/7) ............. 90

Figure 13.3. On-Chip Memory Map for 16 kB Devices (C8051F38C) ..................... 91

Figure 14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ ... 94

Figure 14.2. Multiplexed Configuration Example ..................................................... 98

Figure 14.3. Non-multiplexed Configuration Example ............................................. 99

Figure 14.4. EMIF Operating Modes ..................................................................... 100

Figure 14.5. Non-Multiplexed 16-bit MOVX Timing ............................................... 104

Figure 14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 105

Figure 14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 106

Figure 14.8. Multiplexed 16-bit MOVX Timing ....................................................... 107

8

Rev. 1.4

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