C8051F394 Просмотр технического описания (PDF) - Silicon Laboratories

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C8051F394

50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU

Silicon Laboratories 

C8051F39x/37x

Figure 31.8. Timer 3 8-Bit Mode Block Diagram ................................................... 258

Figure 31.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 259

Figure 31.10. Timer 4 16-Bit Mode Block Diagram ............................................... 263

Figure 31.11. Timer 4 8-Bit Mode Block Diagram ................................................. 264

Figure 31.12. Timer 5 16-Bit Mode Block Diagram ............................................... 268

Figure 31.13. Timer 5 8-Bit Mode Block Diagram ................................................. 269

Figure 32.1. PCA Block Diagram ........................................................................... 273

Figure 32.2. PCA Counter/Timer Block Diagram ................................................... 274

Figure 32.3. PCA Interrupt Block Diagram ............................................................ 275

Figure 32.4. PCA Capture Mode Diagram ............................................................. 277

Figure 32.5. PCA Software Timer Mode Diagram ................................................. 278

Figure 32.6. PCA High-Speed Output Mode Diagram ........................................... 279

Figure 32.7. PCA Frequency Output Mode ........................................................... 280

Figure 32.8. PCA 8-Bit PWM Mode Diagram ........................................................ 281

Figure 32.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 282

Figure 32.10. PCA 16-Bit PWM Mode ................................................................... 283

Figure 32.11. PCA Module 2 with Watchdog Timer Enabled ................................ 284

Figure 32.12. Comparator Clear Function Diagram .............................................. 286

Figure 32.13. CEXn with CPCEn = 1, CPCPOL = 0 .............................................. 286

Figure 32.14. CEXn with CPCEn = 1, CPCPOL = 1 .............................................. 287

Figure 32.15. CEXn with CPCEn = 1, CPCPOL = 0 .............................................. 287

Figure 32.16. CEXn with CPCEn = 1, CPCPOL = 1 .............................................. 287

Figure 33.1. Typical C2 Pin Sharing ...................................................................... 298

10

Preliminary Rev. 0.71

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