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C8051F012

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

VDD

VDD

DGND

DGND

AV+

AV+

AGND

AGND

TCK

TMS

TDI

TDO

/RST

XTAL1

XTAL2

VREF

DAC0

DAC1

AIN0

AIN1

AIN2

AIN3

CP0+

CP0-

Figure 1.3. C8051F002/07/12/17 Block Diagram

Digital Power

C

UART

R

SMBus

O

Analog Power

SPI Bus

S

PCA

S

B

JTAG Boundary Scan

32kbyte

8

FLASH

Timers

A

0,1,2

R

Logic Debug HW

0

5

Reset

1

256 byte

RAM

2048 byte

XRAM

Timer 3

Port 0

S

Latch

W

Port 1

I

VDD

WDT

(F007/17 only)

Latch

T

Monitor

C

C

Port 2

Latch

H

External

Oscillator

Circuit

o

r System Clock

SFR Bus

Internal

e

Oscillator

Port 3

Latch

VREF

DAC0

(12-Bit)

DAC1

(12-Bit)

A

M

Prog

Gain

U

X

TEMP

CP0

ADC

100ksps

CP1

P

P0.0

0

P0.1

P0.2

P0.3

D

P0.4

r

P0.5

v

P0.6

P0.7

P

1

D

r

v

P

2

D

r

v

P

3

D

r

v

11

Rev. 1.7

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