SAA7381 Просмотр технического описания (PDF) - Philips Electronics
Номер в каталоге
Компоненты Описание
производитель
SAA7381 Datasheet PDF : 108 Pages
| |||
Philips Semiconductors
ATAPI CD-R block decoder
Objective specification
SAA7381
2.4 Buffer memory organisation
Memory is mapped as a 16-bit block number and 12-bit
offset into that block. The block oriented memory structure
permits the use of 16-bit pointers in software thereby
minimising the overhead of accessing memory.
The address can be found from the following equation:
address = block number × 2560 + offset.
The microcontroller sees the SAA7381 as a memory
mapped peripheral, with control and status registers
appearing in the upper address space.
The lowest 52 kbytes (48 kbytes + 4 kbytes) of the
8051 microcontroller external address space is mapped as
a window into the memory on a user-specified 1 kbyte
boundary within the buffer RAM. This can be used as a
scratchpad memory.
The next 4 kbytes is separately mapped as a window into
the memory on a user-specified 1 kbyte boundary within
the RAM.
The next 7.5 kbytes of the external data space consists of
three independently addressed memory segments for
accessing block data, subcode information and block
headers.
The registers of the SAA7381 are mapped into the top
256 bytes of external data space.
2.5 Subcode handling features
The writing of data into the buffer RAM is aligned to the
absolute time sync marker with the following features:
• Subcodes are written into memory together with their
associated sector data.This eases the provision of
specialist features, for example CD + G or Karaoke CD
applications.
• All channels of subcode are de-interleaved
• The Q channel is also Cyclic Redundancy Checked
(CRC) for increased reliability
• When operating in 3-wire subcode mode, it is possible
to control or read the P bit in the P-W subcode stream.
2.6 Multimedia output audio control features
The I2S-bus input may be processed before feeding to the
multimedia audio output in several simple ways:
• As audio is transferred via the buffer memory, it is not
necessary to have the CD-DSP I2S-bus input at exactly
the audio n = 1 or video n = 2 rate. Any faster speed will
work because the buffer RAM is used as a FIFO.
• Both channels may be independently controlled. The left
channel output may be sourced from zero (digital
silence), left or right input; this also applies for the right
channel output. This permits basic audio switching and
channel swapping.
• IEC 958 (SPDIF, AES/EBU and DOBM) output with
Q-W subcode and programmable category code, can be
output from the same CD-DSP I2S-bus data source.
3 QUICK REFERENCE DATA
SYMBOL
VDDD(core)
VDDD(pad)
IDDD
fxtal
PARAMETER
digital core supply voltage
digital peripheral supply voltage
supply current
crystal frequency
Tamb
Tstg
operating ambient temperature
storage temperature
MIN.
TYP.
3.0
3.3
VDDD(core) 5.0 or 3.3
tbf
60
8
8.4672, 11.289,
16.9344 or 33.8688
0
−
−55
−
MAX.
3.6
5.0
tbf
35
70
+125
UNIT
V
V
mA
MHz
°C
°C
4 ORDERING INFORMATION
TYPE
NUMBER
SAA7381
PACKAGE
NAME
DESCRIPTION
LQFP144 plastic low profile quad flat package; 144 leads;
body 20 × 20 × 1.4 mm
VERSION
SOT486-1
1997 Aug 12
4
Share Link: 