SAA7381 Просмотр технического описания (PDF) - Philips Electronics

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SAA7381

ATAPI CD-R block decoder

Philips Electronics 

Philips Semiconductors

ATAPI CD-R block decoder

Objective specification

SAA7381

1 FEATURES

• Supports real time error detection and correction in

hardware. Error correction to n = 27, error detect to

n = 30 and raw data transfer to n = 32.

• DVD-ROM supported in combination with the SAA7335

• Direct generic interface to external Small Computer

Systems Interface (SCSI) controller devices

• Operates with up to 16 Mbytes DRAM

– Hyper-page DRAM up to 33 Mbytes words/s burst

– Fast-page DRAM at up to 17.5 Mbytes words/s burst

• Has fixed n = 1 or n = 2 rate (44.1 or 88.2 kHz) I2S-bus

multimedia output for simple audio/video output;

features for CAV/quasi-CLV support

– Supports Philips multimedia audio CODEC

– Provides ‘SHOARMA’ Red Book audio buffer

• IEC 958 (SPDIF, AES/EBU and DOBM) output with

Q-W subcode and programmable category code, output

at n = 1 rate

• Device registers are memory mapped for faster direct

access to the chip

• Provides direct access from sub-CPU to buffer RAM to

support scratchpad accesses. This eliminates the need

for extra RAM chips in the system

• Automatic sequencing of ATAPI packet command

protocol, including command termination

• Automated data transfers to and from the host using

PIO, DMA and ultra DMA.

2 GENERAL DESCRIPTION

The SAA7381 is a block decoder/encoder and buffer

manager for high-speed CD-ROM/CD-R functions, that

integrates real time error correction and detection and

bidirectional ATAPI transfer functions into a single chip.

2.1 Memory mapped control registers

The SAA7381 device has a large number of memory

mapped registers. These are arranged so that high-level

languages see the registers as external byte or 16-bit

integer quantities. The block addressing of the SAA7381

facilitates the use of pairs of 16-bit quantities to represent

addresses.

The reading and writing of 16-bit registers within the device

can be performed by two separate 8-bit reads, where the

second byte data is latched at the same time as the first

byte is read.

2.2 Error correction features

The SAA7381 has an on-chip 36 kbits memory that is used

as a buffer memory for error and erasure correction

processing. This buffer memory reduces the number of

external RAM accesses that are needed for error

correction and thus allows for an increased rate of data

throughput.

The error corrector is switchable between two-pass,

single-pass [both with Error Detection/Correction

(EDC/ECC)] and EDC only modes to further improve

throughput. The presence of the full error corrector

removes the need for firmware based control of the error

corrector’s operation.

2.3 Host interface features

The SAA7381 has an ATAPI host interface that may be

directly connected to the ATAPI bus thereby reducing the

need for external support devices. It supports PIO Mode 4

transfer and Mode 0 ultra DMA. This interface can also be

configured as a generic DMA interface for use with

external host interface devices (e.g. SCSI controller).

The DMA interface has the following features:

• ATAPI command packets are automatically loaded into

the command FIFO

• Data transfer to the host is automatically sequenced to

reduce inter-block latencies and improve host CPU

utilisation

• Host data transfer rate is independent of error corrector

operation and the data input path

• The host interface features automatic determination of

block length for Mode 2, Form 1 and Form 2 sectors.

The block length transferred is programmable.

• The host interface can transfer up to 3 sub-blocks per

sector, with each sub-block being transferred dependent

on the Form bit. Automatic reload of sub-block pointers

and unconditional transfer are supported.

1997 Aug 12

3

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