VN16117L1 Просмотр технического описания (PDF) - Vaishali Semiconductor
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VN16117L1 Datasheet PDF : 15 Pages
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VN16117
Preliminary
Table 5. DC Electrical Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
VIH,TTL
TTL Input High Voltage Level, Guaranteed High Signal for
All Inputs
Min.
2
Typ.
Max. Unit
5.5 V
VIL,TTL
TTL Input Low Voltage Level, Guaranteed Low Signal for 0
All Inputs
0.8 V
VOH,TTL
TTL Output High Voltage Level, IOH = -400 µA
2.2
VCC
V
VOL,TTL
TTL Output Low Voltage Level, IOL = 1 mA
0
0.6 V
IIH,TTL
Input High Current, VIN = 2.4 V, VCC = 3.45 V
40
µA
IIL,TTL
Input Low Current, VIN = 0.4 V, VCC = 3.45 V
-600 µA
ICC,TRX[1,2] Transceiver VCC Supply Current, TA = 25°C
220
mA
Note:
1. Measurement Conditions: Tested sending 1062.5 MBd PRBS 27-1 sequence from a serial Bit Error Rate Tester
(BERT) with DOUT± outputs terminated with 150Ω resistors to GND.
2. Typical values are at Vcc = 3.3 volts.
Table 6. Transceiver Reference Clock Requirements
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
F
Nominal Frequency (for Fiber Channel Compliance)
Ftol
Frequency Tolerance
Symm
Symmetry (Duty Cycle)
Min.
106.20
-100
40
Typ.
106.25
Max.
106.30
+100
60
Unit
MHz
ppm
%
Table 7. Transmitter Timing Characteristics
TA = 0°C to +70°C, Vcc = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time to Rising Edge of REFCLK
Min.
2.0
Typ.
Max.
Unit
nsec
thold
T_txlat[1]
Hold Time to Rising Edge of REFCLK
Transmitter Latency
1.5
3.5
nsec
nsec
4.4
bits
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data
word (as triggered by the rising edge of the transmit by clock, REFCLK) and the transmission of the first serial bit
of that parallel word (defined by the rising edge of the first bit transmitted).
2001-08-09
Page 8
MDSN-0002-02
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
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