M48T212Y-85MH1(2000) Просмотр технического описания (PDF) - STMicroelectronics
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M48T212Y-85MH1 Datasheet PDF : 23 Pages
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M48T212Y, M48T212V
READ MODE
The M48T212Y/V executes a read cycle whenev-
er W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
the address presented to the M48T212Y/V is in
the range of 0h-Fh, one of the on-board TIME-
KEEPER registers is accessed and valid data will
be available to the eight data output drivers within
tAVQV after the address input signal is stable, pro-
viding that the E and G access times are also sat-
isfied.If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either tELQV for E or
tGLQV for G rather than the address access time.
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 7. Read Cycle Timing: RTC Control Signals
ADDRESS
E
G
READ
tAVAV
tELQV
tELQX
tGLQV
READ
tAVAV
tAVQV
WRITE
tAVAV
tAVWL
tWHAX
tWLWH
W
DQ7-DQ0
tGLQX
tAXQX
DATA OUT
VALID
DATA OUT
VALID
tGHQZ
DATA IN
VALID
AI02640
Table 10. Read Mode Characteristics
(TA = 0 to 70°C)
Symbol
Parameter
tAVAV Read Cycle Time
tAVQV Address Valid to Output Valid
tELQV Chip Enable Low to Output Valid
tGLQV Output Enable Low to Output Valid
tELQX (1) Chip Enable Low to Output Transition
tGLQX (1) Output Enable Low to Output Transition
tEHQZ (1) Chip Enable High to Output Hi-Z
tGHQZ (1) Output Enable High to Output Hi-Z
tAXQX Address Transition to Output Transition
Note: 1. CL = 5pF
M48T212Y
M48T212V
-70
-85
Unit
Min
Max
Min
Max
70
85
ns
70
85
ns
70
85
ns
25
35
ns
5
5
ns
0
0
ns
20
25
ns
20
25
ns
5
5
ns
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