M48T212Y-85MH1(2000) Просмотр технического описания (PDF) - STMicroelectronics
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M48T212Y-85MH1 Datasheet PDF : 23 Pages
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M48T212Y, M48T212V
WRITE MODE
The M48T212Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of tEHAX from Chip Enable
or tWHAX from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
tDVWH prior to the end of write and remain valid for
tWHDX afterward.
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data will be written into the device. When EX is low
(and E is high) an external SRAM location is se-
lected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 8. Write Cycle Timing: RTC Control Signals
ADDRESS
tAVEL
E
G
tAVWL
WRITE
tAVAV
WRITE
tAVAV
READ
tAVAV
tAVEH
tELEH
tAVWH
tEHAX tWHAX
tAVQV
tGLQV
tEHDX
tWLWH
tWHQX
tWLQZ
W
DQ0-DQ7
DATA OUT
VALID
tEHQZ
tDVEH tDVWH
DATA IN
VALID
DATA IN
VALID
tWHDX
DATA OUT
VALID
AI02641
10/23
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