CY7C43663AV-10AC Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CY7C43663AV-10AC

3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43663AV

CY7C43643AV

CY7C43683AV

CY7C436X3AV, respectively. The highest numbered input is

used as the most significant bit of the binary number in each

case. Valid programming values for the registers range from

0 – 1023 for the CY7C43643AV, 0 – 4095 for the

CY7C43663AV, and 0 – 16383 for the CY7C43683AV.[2]

Before programming the offset registers, FF/IR is set HIGH.

FIFOs begin normal operation after programming is complete.

To program the X and Y registers serially, initiate a Master

Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH

during the LOW-to-HIGH transition of MRS1, MRS2. After this

reset is complete, the X and Y register values are loaded

bit-wise through the FS0/SD input on each LOW-to-HIGH

transition of CLKA that the FS1/SEN input is LOW. Twenty,

twenty- four, or twenty-eight bit writes are needed to complete

the programming for the CY7C436X3AV, respectively. The two

registers are written in the order Y then finally X. The first-bit

Write stores the most significant bit of the Y register and the

last-bit Write stores the least significant bit of the X register.

Each register value can be programmed from 0 – 1023

(CY7C43643AV), 0 – 4095 (CY7C43663AV), and 0 – 16383

(CY7C43683AV).

When the option to program the offset registers serially is

chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW

until all register bits are written. FF/IR is set HIGH by the

LOW-to-HIGH transition of CLKA after the last bit is loaded to

allow normal FIFO operation.

SPM, FS0/SD, and FS1/SEN function the same way in both

CY Standard and FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A0–35 lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A0–35 lines are active mail2

register outputs when both CSA and W/RA are LOW.

Data is loaded into the FIFO from the A0–35 inputs on a

LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is

HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see

Table 2). FIFO writes on Port A are independent of any

concurrent Port B operation.

The Port B control signals are identical to those of Port A with

the exception that the Port B Write/Read select (W/RB) is the

inverse of the Port A Write/Read select (W/RA). The state of

the Port B data (B0–35) lines is controlled by the Port B Chip

Select (CSB) and Port B Write/Read select (W/RB). The B0–35

lines are in the high-impedance state when either CSB is HIGH

or W/RB is LOW. The B0–35 lines are active outputs when CSB

is LOW and W/RB is HIGH.

Data is read from the FIFO to the B0–35 outputs by a

LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is

HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see

Table 3). FIFO reads and writes on Port B are independent of

any concurrent Port A operation.

The set-up and hold time constraints to the port clocks for the

port Chip Selects and Write/Read Selects are only for enabling

Write and Read operations and are not related to

high-impedance control of the data outputs. If a port enable is

LOW during a clock cycle, the port’s Chip Select and

Write/Read Select may change states during the set-up and

hold time window of the cycle.

When operating the FIFO in FWFT Mode with the Output

Ready flag LOW, the next word written is automatically sent to

the FIFO’s output register by the LOW-to-HIGH transition of

the port clock that sets the Output Ready flag HIGH, data

residing in the FIFO’s memory array is clocked to the output

register only when a Read is selected using the port’s Chip

Select, Write/Read Select, Enable, and Mailbox Select.

When operating the FIFO in CY Standard mode, regardless of

whether the Empty Flag is LOW or HIGH, data residing in the

FIFO’s memory array is clocked to the output register only

when a Read is selected using the port’s Chip Select,

Write/Read Select, Enable, and Mailbox Select.

Synchronized FIFO Flags

Each FIFO is synchronized to its port clock through at least two

flip-flop stages. This is done to improve flag-signal reliability by

reducing the probability of the metastable events when CLKA

and CLKB operate asynchronously to one another. EF/OR and

AE are synchronized to CLKB. FF/IR and AF are synchronized

to CLKA. Table 4 shows the relationship of each port flag to

the FIFO.

Empty/Output Ready Flags (EF/OR)

These are dual-purpose flags. In the FWFT Mode, the Output

Ready (OR) function is selected. When the Output Ready flag

is HIGH, new data is present in the FIFO output register. When

the Output Ready flag is LOW, the previous data word remains

in the FIFO output register and any FIFO reads are ignored.

In the CY Standard mode, the Empty Flag (EF) function is

selected. When the Empty Flag is HIGH, data is available in

the FIFO’s RAM memory for reading to the output register.

When Empty Flag is LOW, the previous data word remains in

the FIFO output register and any FIFO reads are ignored.

The Empty/Output Ready flag of a FIFO is synchronized to

CLKB. For both the FWFT and CY Standard modes, the FIFO

Read pointer is incremented each time a new word is clocked

to its output register. The state machine that controls an Output

Ready flag monitors a Write pointer and Read pointer

comparator that indicates when the FIFO SRAM status is

empty, empty + 1, or empty + 2.

In FWFT Mode, from the time a word is written to a FIFO, it

can be shifted to the FIFO output register in a minimum of

three cycles of the Output Ready flag synchronizing clock.

Therefore, an Output Ready flag is LOW if a word in memory

is the next data to be sent to the FIFO output register and three

cycles have not elapsed since the time the word was written.

The Output Ready flag of the FIFO remains LOW until the third

LOW-to-HIGH transition of the synchronizing clock occurs,

simultaneously forcing the Output Ready flag HIGH and

shifting the word to the FIFO output register.

In the CY Standard mode, from the time a word is written to a

FIFO, the Empty flag will indicate the presence of data

available for reading in a minimum of two cycles of the Empty

flag synchronizing clock. Therefore, an Empty flag is LOW if a

word in memory is the next data to be sent to the FIFO output

register and two cycles have not elapsed since the time the

word was written. The Empty flag of the FIFO remains LOW

until the second LOW-to-HIGH transition of the synchronizing

clock occurs, forcing the Empty flag HIGH; only then can data

be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag

synchronizing clock begins the first synchronization cycle of a

Document #: 38-06024 Rev. *C

Page 7 of 28

Share Link: