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CY7C43643AV

3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43663AV

CY7C43643AV

CY7C43683AV

Signal Description

Master Reset (MRS1, MRS2)

The FIFO memory of the CY7C436X3AV undergoes a

complete reset by taking its associated Master Reset (MRS1,

MRS2) input LOW for at least four Port A clock (CLKA) and

four Port B clock (CLKB) LOW-to-HIGH transitions. The

Master Reset input can switch asynchronously to the clocks.

A Master Reset initializes the internal Read and Write pointers

and forces the Full/Input Ready flag (FF/IR) LOW, the

Empty/Output Ready flag (EF/OR) LOW, the Almost Empty

flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Master

Reset also forces the Mailbox flag (MBF1, MBF2) of the

parallel mailbox register HIGH. After a Master Reset, the

FIFO’s Full/Input Ready flag is set HIGH after two clock cycles

to begin normal operation. A Master Reset must be performed

on the FIFO after power up, before data is written to its

memory.

A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,

MRS2) input latches the value of the Big Endian (BE) input,

determining the order by which bytes are transferred through

Port B.

A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)

input latches the values of the Flag Select (FS0, FS1) and

Serial Programming Mode (SPM) inputs for choosing the

Almost Full and Almost Empty offset programming method

(see Almost Empty and Almost Full flag offset programming

below).

Partial Reset (PRS)

The FIFO memory of the CY7C436X3AV undergoes a limited

reset by taking its associated Partial Reset (PRS) input LOW

for at least four Port A clock (CLKA) and four Port B clock

(CLKB) LOW-to-HIGH transitions. The Partial Reset inputs

can switch asynchronously to the clocks. A Partial Reset

initializes the internal Read and Write pointers and forces the

Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready

flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the

Almost Full flag (AF) HIGH. A Partial Reset also forces the

Mailbox flag (MBF1, MBF2) of the parallel mailbox register

HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag

is set HIGH after two clock cycles to begin normal operation.

Whatever flag offsets, programming method (parallel or

serial), and timing mode (FWFT or CY Standard mode) are

currently selected at the time a Partial Reset is initiated, those

settings will remain unchanged upon completion of the reset

operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Master Reset would be

inconvenient.

Big Endian/First-Word Fall-Through (BE/FWFT)

This is a dual-purpose pin. At the time of Master Reset, the BE

select function is active, permitting a choice of Big or Little

Endian byte arrangement for data written to or Read from

Port B. This selection determines the order by which bytes (or

words) of data are transferred through this port. For the

following illustrations, assume that a byte (or word) bus size

has been selected for Port B.

A HIGH on the BE/FWFT input when the Master Reset (MRS1,

MRS2) inputs go from LOW to HIGH will select a Big Endian

arrangement. When data is moving in the direction from Port

A to Port B, the most significant byte (word) of the long-word

written to Port A will be transferred to Port B first; the least

significant byte (word) of the long-word written to Port A will be

transferred to Port B last.

A LOW on the BE/FWFT input when the Master Reset (MRS1,

MRS2) inputs go from LOW to HIGH will select a Little Endian

arrangement. When data is moving in the direction from Port

A to Port B, the least significant byte (word) of the long-word

written to Port A will be transferred to Port B first; the most

significant byte (word) of the long-word written to Port A will be

transferred to Port B last.

After Master Reset, the FWFT select function is active,

permitting a choice between two possible timing modes: CY

Standard mode or First-Word Fall-Through (FWFT) Mode.

Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH

on the BE/FWFT input at the second LOW-to-HIGH transition

of CLKA will select CY Standard mode. This mode uses the

Empty Flag function (EF) to indicate whether or not there are

any words present in the FIFO memory. It uses the Full Flag

function (FF) to indicate whether or not the FIFO memory has

any free space for writing. In CY Standard mode, every word

read from the FIFO, including the first, must be requested

using a formal Read operation.

Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW

on the BE/FWFT input of the second LOW-to-HIGH transition

of CLKA will select FWFT Mode. This mode uses the Output

Ready function (OR) to indicate whether or not there is valid

data at the data outputs (B0–35). It also uses the Input Ready

(IR) function to indicate whether or not the FIFO memory has

any free space for writing. In the FWFT mode, the first word

written to an empty FIFO goes directly to data outputs, no

Read request necessary. Subsequent words must be

accessed by performing a formal Read operation.

Following Master Reset, the level applied to the BE/FWFT

input to choose the desired timing mode must remain static

throughout the FIFO operation.

Programming the Almost Empty and Almost Full Flags

Two registers in the CY7C436X3AV are used to hold the offset

values for the Almost Empty and Almost Full flags. The Port B

Almost Empty flag (AE) offset register is labeled X. The Port A

Almost Full flag (AF) offset register is labeled Y. The index of

each register name corresponds with preset values during the

reset of a FIFO, programmed in parallel using the FIFO’s Port

A data inputs, or programmed in serial using the Serial Data

(SD) input (see Table 1).

To load a FIFO’s Almost Empty flag and Almost Full flag offset

registers with one of the three preset values listed in Table 1,

the Serial Program Mode (SPM) and at least one of the

flag-select inputs must be HIGH during the LOW-to-HIGH

transition of its Master Reset input (MRS1, MRS2). For

example, to load the preset value of 64 into X and Y, SPM, FS0

and FS1 must be HIGH when the FIFO reset (MRS1, MRS2)

returns HIGH. When using one of the preset values for the flag

offsets, the FIFO can be reset simultaneously or at different

times.

To program the X and Y registers from Port A, perform a

Master Reset on both FIFOs simultaneously with SPM HIGH

and FS0 and FS1 LOW during the LOW-to-HIGH transition of

MRS1, MRS2. After this reset is complete, the first two writes

to the FIFO do not store data in RAM but load the offset

registers in the order Y and X. The Port A data inputs used by

the offset registers are (A0–9), (A0–11), or (A0–13), for the

Document #: 38-06024 Rev. *C

Page 6 of 28

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