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BD8105FV Просмотр технического описания (PDF) - ROHM Semiconductor

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BD8105FV Datasheet PDF : 13 Pages
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BD8105FV
Technical Note
3Enable Signal
By applying voltage at least VCC×0.8 or more to the SDWN terminal, D0 (16 pin)~D11 (4 pin) become open forcibly.
At this time, the temperature protection circuit (TSD) stops. D11D0 become PWM operation by inputting PWM to
SDWN(3 pin).
4SEROUT
A cascade connection can be made (connecting at least 2 or more IC’s in serial).
Serial signal input from SERIN is transferred into receiver IC by the fall edge of the CLK signal.
Since this functionality gives enough margins for the setup time prior to the rise edge of the CLK signal on the receiver
IC (using the exact same CLK signal of sender IC), the application reliability can be improved as cascade connection
functionality.
LATCH
SERIN
CLK
SEROUT
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
1 2 3 4 5 6 7 8 9 10 11 12 13
D11
Fig.14
Cascade Connection
By using (at least) 2 ICs, each IC’s D11~D0, at (at least) 24ch, can be controlled by the 24-bit SERIN signal. The serial
data input to the sender IC can be transferred to the receiver IC by inputting 12CLK to the CLK terminal.
LATCH
SERIN
CLK
Send side IC
Receive side IC
d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Fig.15
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© 2009 ROHM Co., Ltd. All rights reserved.
7/12
2009.07 - Rev.B

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