BCM1122 Просмотр технического описания (PDF) - Broadcom Corporation
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BCM1122 Datasheet PDF : 2 Pages
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OVERVIEW
1 Gbps
JTAG
Debug/
Trace
GPIO/
Interrupt/
PCMCIA
Dual
SMBus
Generic
Bus and
Flash I/O
Data Mover SB-1
128K
Core L2 Cache
256 Bits
ZBbus
200MHz clock; 51 Gbps bandwidth
DDR
Memory
Controller
Serial
Interface
10/100/
1000
MAC
10/100/
MAC
8-Bit FIFO
32-Bit
PCI
Serial
Interface
13 Gbps
55 Gbps
55 Gbps
2.1 Gbps
Broadcom’s BCM1122 is a state-of-the-art processor solution targeted
at the fast-growing networking, wireless communications, storage,
server/networking appliance and imaging markets. The BCM1122
offers industry-leading performance, high functional integration, and
low power levels in a small package required by next-generation
networking applications.
The BCM1122 is software-compatible with the BCM1125H and the
dual-processor BCM1250 and share development and modeling tools,
firmware, and operating systems. The BCM1122 is an intelligent
system-on-a-chip consisting of a Broadcom SB-1 high performance
MIPS64 CPU, a shared 128-KB L2 cache, a DDR memory controller,
and an integrated I/O. All major blocks of the processor are connected
together via the ZBbus, a high-speed, low-latency, split-transaction,
memory-coherent bus. The bus implements the standard MESI protocol
to ensure coherency between the CPU, L2 cache, I/O agents, and
memory.
One Gigabit Ethernet MAC (10/100/1000) and one Fast Ethernet MAC
(10/100) enable easy interfacing to LANs as well as connecting to data
plane components over the Ethernet or packet FIFO interface. In cases
where Ethernet protocol processing is not required, the Gigabit Ethernet
MAC can be configured as an 8-bit packet FIFO. High-speed I/O is
provided using a 66-MHz (rev 2.2) PCI local bus.
Two serial ports are provided for WAN connections at up to T3/OC-1
rates (55 Mbps). To enable low-chip-count systems, the BCM1122
processors also include a configurable generic bus that allows glueless
connection of a boot ROM or FLASH memory and simple I/O
peripherals. On-chip debugging, tracing, and performance monitoring
functions assist both hardware and software designers in debugging and
tuning the system. The system can be run in either big- or little-endian
mode. The BCM1122 is manufactured in TSMC's 0.13-µ process, and is
packaged in pin-compatible 31-mm BGA package that is pin-compatible
with the BCM1125H.
Implementation of MIPS64 ISA
The SB-1 CPU core is a high-performance implementation of the
standard MIPS64 Instruction Set Architecture (ISA), and incorporates
the MIPS-3D and MIPS-MDMX Application Specific Extensions
(ASEs). The core supports a four-issue enhanced skew pipeline and can
dispatch up to two memory and two ALU (Integer, Floating Point,
MDMX or MIPS-3D) instructions per cycle.
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
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BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
1122-PB00-R
05/19/04
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
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