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BCM5691_

A Scalable Approach to Gigabit Ethernet

Broadcom Corporation 

White Paper

06/27/02

■ BCM567x/BCM569x

With the StrataXGS family, Broadcom has improved the StrataSwitch architecture in several ways:

• The depth of IP address tables and routing information has been significantly increased.

• Switches that can store more route entries can support a greater number of attached devices.

• StrataXGS family of components uses a widely used approach called hashing, which increases table lookup

performance compared with binary search capabilities.

• Broadcom has built a special 10-Gbps chip-to-chip interface, which improves Scalability and performance.

QUALITY OF SERVICE

StrataXGS chips offer extensive support for packet classification, marking, and prioritization to enable QoS support. QoS on

the LAN is increasingly a checklist item for enterprise customers, who are beginning to run latency-sensitive applications

such as VoIP locally. End customers might also want to ensure the integrity of high-priority data applications and enforce

access control lists (ACLs).

By leveraging the HiGig interface, class-of-service markings and QoS can be integrated across a stack of chips used to build

a system so that markings are not lost when packets are passed from one component to another. All StrataXGS chip ports

support eight CoS queues into which traffic with different priority weights can be placed.

HIGIG™ INTERFACE

New to the Broadcom product family is a 10-Gbps, full-duplex chip-to-chip interface that enhances system scalability and

performance, called the HiGig interface. It adds an 8-byte header to the Layer 2 GE frame as it exits the interface. This

header contains information about the packet, its source and destination ports, and port mirroring. This information hastens

table lookups when two Broadcom components are connected together, thus improving overall system performance.

The HiGig interface allows the interconnection of several StrataXGS chip modules to form systems with different port

densities. Communication between the CPUs, a process called stacking, is performed in-band via the HiGig header using

special master/slave protocols developed by Broadcom. Link aggregation, port mirroring, and class-of-service markings are

fully supported across the interconnected modules at wire speeds.

INTEGRATED SERIALIZER/DESERIALIZER (SERDES)

A SerDes interface—which converts data from a parallel bus into a serial stream—is integrated onto each port of each

StrataXGS chip. This design precludes connections to external SerDes chips, simplifying design.

The integrated SerDes support, CoS functions, Broadcom API, and other StrataXGS features are described in more detail

in the section, “StrataXGS Features and Benefits in Depth.”

Document 567x_569x-WP100-R

Broadcom Corporation

StrataXGS Gigabit Ethernet Architecture

Page 3

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